2 * Copyright (c) 2014 Google, Inc
4 * From Coreboot src/lib/ramtest.c
6 * SPDX-License-Identifier: GPL-2.0
13 static void write_phys(unsigned long addr, u32 value)
19 : "r" (addr), "r" (value) /* inputs */
27 static u32 read_phys(unsigned long addr)
32 static void phys_memory_barrier(void)
35 /* Needed for movnti */
50 void quick_ram_check(void)
55 backup = read_phys(CONFIG_RAMBASE);
56 write_phys(CONFIG_RAMBASE, 0x55555555);
57 phys_memory_barrier();
58 if (read_phys(CONFIG_RAMBASE) != 0x55555555)
60 write_phys(CONFIG_RAMBASE, 0xaaaaaaaa);
61 phys_memory_barrier();
62 if (read_phys(CONFIG_RAMBASE) != 0xaaaaaaaa)
64 write_phys(CONFIG_RAMBASE, 0x00000000);
65 phys_memory_barrier();
66 if (read_phys(CONFIG_RAMBASE) != 0x00000000)
68 write_phys(CONFIG_RAMBASE, 0xffffffff);
69 phys_memory_barrier();
70 if (read_phys(CONFIG_RAMBASE) != 0xffffffff)
73 write_phys(CONFIG_RAMBASE, backup);
75 post_code(POST_RAM_FAILURE);
76 panic("RAM INIT FAILURE!\n");
78 phys_memory_barrier();