3 * Graeme Russ, <graeme.russ@gmail.com>
6 * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
8 * SPDX-License-Identifier: GPL-2.0+
12 * This file provides the interrupt handling functionality for systems
13 * based on the standard PC/AT architecture using two cascaded i8259
14 * Programmable Interrupt Controllers.
19 #include <asm/i8259.h>
20 #include <asm/ibmpc.h>
21 #include <asm/interrupt.h>
23 #if CONFIG_SYS_NUM_IRQS != 16
24 #error "CONFIG_SYS_NUM_IRQS must equal 16 if CONFIG_SYS_NUM_IRQS is defined"
27 int interrupt_init(void)
33 /* Mask all interrupts */
34 outb(0xff, MASTER_PIC + IMR);
35 outb(0xff, SLAVE_PIC + IMR);
38 /* Place master PIC interrupts at INT20 */
39 /* ICW3, One slave PIC is present */
40 outb(ICW1_SEL|ICW1_EICW4, MASTER_PIC + ICW1);
41 outb(0x20, MASTER_PIC + ICW2);
42 outb(IR2, MASTER_PIC + ICW3);
43 outb(ICW4_PM, MASTER_PIC + ICW4);
45 for (i = 0; i < 8; i++)
46 outb(OCW2_SEOI | i, MASTER_PIC + OCW2);
49 /* Place slave PIC interrupts at INT28 */
51 outb(ICW1_SEL|ICW1_EICW4, SLAVE_PIC + ICW1);
52 outb(0x28, SLAVE_PIC + ICW2);
53 outb(0x02, SLAVE_PIC + ICW3);
54 outb(ICW4_PM, SLAVE_PIC + ICW4);
56 for (i = 0; i < 8; i++)
57 outb(OCW2_SEOI | i, SLAVE_PIC + OCW2);
60 * Enable cascaded interrupts by unmasking the cascade IRQ pin of
65 /* Interrupt 9 should be level triggered (SCI). The OS might do this */
66 configure_irq_trigger(9, true);
68 /* Initialize core interrupt and exception functionality of CPU */
69 cpu_init_interrupts();
76 void mask_irq(int irq)
80 if (irq >= CONFIG_SYS_NUM_IRQS)
84 imr_port = SLAVE_PIC + IMR;
86 imr_port = MASTER_PIC + IMR;
88 outb(inb(imr_port) | (1 << (irq & 7)), imr_port);
91 void unmask_irq(int irq)
95 if (irq >= CONFIG_SYS_NUM_IRQS)
99 imr_port = SLAVE_PIC + IMR;
101 imr_port = MASTER_PIC + IMR;
103 outb(inb(imr_port) & ~(1 << (irq & 7)), imr_port);
106 void specific_eoi(int irq)
108 if (irq >= CONFIG_SYS_NUM_IRQS)
113 * IRQ is on the slave - Issue a corresponding EOI to the
114 * slave PIC and an EOI for IRQ2 (the cascade interrupt)
117 outb(OCW2_SEOI | (irq & 7), SLAVE_PIC + OCW2);
121 outb(OCW2_SEOI | irq, MASTER_PIC + OCW2);
127 void configure_irq_trigger(int int_num, bool is_level_triggered)
129 u16 int_bits = inb(ELCR1) | (((u16)inb(ELCR2)) << 8);
131 debug("%s: current interrupts are 0x%x\n", __func__, int_bits);
132 if (is_level_triggered)
133 int_bits |= (1 << int_num);
135 int_bits &= ~(1 << int_num);
137 /* Write new values */
138 debug("%s: try to set interrupts 0x%x\n", __func__, int_bits);
139 outb((u8)(int_bits & 0xff), ELCR1);
140 outb((u8)(int_bits >> 8), ELCR2);
142 #ifdef PARANOID_IRQ_TRIGGERS
144 * Try reading back the new values. This seems like an error but is
147 if (inb(ELCR1) != (int_bits & 0xff)) {
148 printf("%s: lower order bits are wrong: want 0x%x, got 0x%x\n",
149 __func__, (int_bits & 0xff), inb(ELCR1));
152 if (inb(ELCR2) != (int_bits >> 8)) {
153 printf("%s: higher order bits are wrong: want 0x%x, got 0x%x\n",
154 __func__, (int_bits>>8), inb(ELCR2));