1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright 2019 Google LLC
8 #include <binman_sym.h>
14 #include <spi_flash.h>
15 #include <asm/intel_pinctrl.h>
16 #include <dm/uclass-internal.h>
17 #include <asm/fsp2/fsp_internal.h>
19 int arch_cpu_init_dm(void)
25 /* Make sure pads are set up early in U-Boot */
26 if (spl_phase() != PHASE_BOARD_F)
29 /* Probe all pinctrl devices to set up the pads */
30 ret = uclass_first_device_err(UCLASS_PINCTRL, &dev);
32 return log_msg_ret("no fsp pinctrl", ret);
33 node = ofnode_path("fsp");
34 if (!ofnode_valid(node))
35 return log_msg_ret("no fsp params", -EINVAL);
36 ret = pinctrl_config_pads_for_node(dev, node);
38 return log_msg_ret("pad config", ret);
43 #if !defined(CONFIG_TPL_BUILD)
44 binman_sym_declare(ulong, intel_fsp_m, image_pos);
45 binman_sym_declare(ulong, intel_fsp_m, size);
48 * get_cbfs_fsp() - Obtain the FSP by looking up in CBFS
50 * This looks up an FSP in a CBFS. It is used mostly for testing, when booting
51 * U-Boot from a hybrid image containing coreboot as the first-stage bootloader.
53 * The typical use for this feature is when building a Chrome OS image which
54 * includes coreboot in it. By adding U-Boot into the 'COREBOOT' CBFS as well,
55 * it is possible to make coreboot chain-load U-Boot. Thus the initial stages of
56 * the SoC init can be done by coreboot and the later stages by U-Boot. This is
57 * a convenient way to start the porting work. The jump to U-Boot can then be
58 * moved progressively earlier and earlier, until U-Boot takes over all the init
59 * and you have a native port.
61 * This function looks up a CBFS at a known location and reads the FSP-M from it
62 * so that U-Boot can init the memory.
64 * This function is not used in the normal boot but is kept here for future
67 * @type; Type to look up (only FSP_M supported at present)
68 * @map_base: Base memory address for mapped SPI
69 * @entry: Returns an entry containing the position of the FSP image
71 static int get_cbfs_fsp(enum fsp_type_t type, ulong map_base,
72 struct binman_entry *entry)
75 * Use a hard-coded position of CBFS in the ROM for now. It would be
76 * possible to read the position using the FMAP in the ROM, but since
77 * this code is only used for development, it doesn't seem worth it.
78 * Use the 'cbfstool <image> layout' command to get these values, e.g.:
79 * 'COREBOOT' (CBFS, size 1814528, offset 2117632).
81 ulong cbfs_base = 0x205000;
82 ulong cbfs_size = 0x1bb000;
83 struct cbfs_priv *cbfs;
86 ret = cbfs_init_mem(map_base + cbfs_base, cbfs_size, &cbfs);
90 const struct cbfs_cachenode *node;
92 node = cbfs_find_file(cbfs, "fspm.bin");
94 return log_msg_ret("fspm node", -ENOENT);
96 entry->image_pos = (ulong)node->data;
97 entry->size = node->data_length;
103 int fsp_locate_fsp(enum fsp_type_t type, struct binman_entry *entry,
104 bool use_spi_flash, struct udevice **devp,
105 struct fsp_header **hdrp, ulong *rom_offsetp)
107 ulong mask = CONFIG_ROM_SIZE - 1;
109 ulong rom_offset = 0;
116 * Find the devices but don't probe them, since we don't want to
117 * auto-config PCI before silicon init runs
119 ret = uclass_find_first_device(UCLASS_NORTHBRIDGE, &dev);
121 return log_msg_ret("Cannot get northbridge", ret);
122 if (!use_spi_flash) {
125 /* Just use the SPI driver to get the memory map */
126 ret = uclass_find_first_device(UCLASS_SPI_FLASH, &sf);
128 return log_msg_ret("Cannot get SPI flash", ret);
129 ret = dm_spi_get_mmap(sf, &map_base, &map_size, &offset);
131 return log_msg_ret("Could not get flash mmap", ret);
134 if (spl_phase() >= PHASE_BOARD_F) {
136 return -EPROTONOSUPPORT;
137 ret = binman_entry_find("intel-fsp-s", entry);
139 return log_msg_ret("binman entry", ret);
141 rom_offset = (map_base & mask) - CONFIG_ROM_SIZE;
146 * Support using a hybrid image build by coreboot. See
147 * the function comments for details
149 ret = get_cbfs_fsp(type, map_base, entry);
151 ulong mask = CONFIG_ROM_SIZE - 1;
154 return -EPROTONOSUPPORT;
155 entry->image_pos = binman_sym(ulong, intel_fsp_m,
157 entry->size = binman_sym(ulong, intel_fsp_m, size);
158 if (entry->image_pos != BINMAN_SYM_MISSING) {
161 entry->image_pos &= mask;
163 entry->image_pos += (map_base & mask);
170 return log_msg_ret("Cannot find FSP", ret);
171 entry->image_pos += rom_offset;
174 * Account for the time taken to read memory-mapped SPI flash since in
175 * this case we don't use the SPI driver and BOOTSTAGE_ID_ACCUM_SPI.
178 bootstage_start(BOOTSTAGE_ID_ACCUM_MMAP_SPI, "mmap_spi");
179 ret = fsp_get_header(entry->image_pos, entry->size, use_spi_flash,
182 bootstage_accum(BOOTSTAGE_ID_ACCUM_MMAP_SPI);
184 return log_msg_ret("fsp_get_header", ret);
187 *rom_offsetp = rom_offset;