1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
10 #include <asm/fsp/fsp_support.h>
12 #include <asm/mrccache.h>
16 DECLARE_GLOBAL_DATA_PTR;
18 int fsp_scan_for_ram_size(void)
20 phys_size_t ram_size = 0;
21 const struct hob_header *hdr;
22 struct hob_res_desc *res_desc;
24 hdr = gd->arch.hob_list;
25 while (!end_of_hob(hdr)) {
26 if (hdr->type == HOB_TYPE_RES_DESC) {
27 res_desc = (struct hob_res_desc *)hdr;
28 if (res_desc->type == RES_SYS_MEM ||
29 res_desc->type == RES_MEM_RESERVED)
30 ram_size += res_desc->len;
32 hdr = get_next_hob(hdr);
35 gd->ram_size = ram_size;
41 int dram_init_banksize(void)
43 const struct hob_header *hdr;
44 struct hob_res_desc *res_desc;
48 if (!ll_boot_init()) {
49 gd->bd->bi_dram[0].start = 0;
50 gd->bd->bi_dram[0].size = gd->ram_size;
52 mtrr_add_request(MTRR_TYPE_WRBACK, 0, gd->ram_size);
57 for (bank = 1, hdr = gd->arch.hob_list;
58 bank < CONFIG_NR_DRAM_BANKS && !end_of_hob(hdr);
59 hdr = get_next_hob(hdr)) {
60 if (hdr->type != HOB_TYPE_RES_DESC)
62 res_desc = (struct hob_res_desc *)hdr;
63 if (res_desc->type != RES_SYS_MEM &&
64 res_desc->type != RES_MEM_RESERVED)
66 if (res_desc->phys_start < (1ULL << 32)) {
67 low_end = max(low_end,
68 res_desc->phys_start + res_desc->len);
72 gd->bd->bi_dram[bank].start = res_desc->phys_start;
73 gd->bd->bi_dram[bank].size = res_desc->len;
74 mtrr_add_request(MTRR_TYPE_WRBACK, res_desc->phys_start,
76 log_debug("ram %llx %llx\n", gd->bd->bi_dram[bank].start,
77 gd->bd->bi_dram[bank].size);
80 /* Add the memory below 4GB */
81 gd->bd->bi_dram[0].start = 0;
82 gd->bd->bi_dram[0].size = low_end;
84 mtrr_add_request(MTRR_TYPE_WRBACK, 0, low_end);
89 unsigned int install_e820_map(unsigned int max_entries,
90 struct e820_entry *entries)
92 unsigned int num_entries = 0;
93 const struct hob_header *hdr;
94 struct hob_res_desc *res_desc;
96 hdr = gd->arch.hob_list;
98 while (!end_of_hob(hdr)) {
99 if (hdr->type == HOB_TYPE_RES_DESC) {
100 res_desc = (struct hob_res_desc *)hdr;
101 entries[num_entries].addr = res_desc->phys_start;
102 entries[num_entries].size = res_desc->len;
104 if (res_desc->type == RES_SYS_MEM)
105 entries[num_entries].type = E820_RAM;
106 else if (res_desc->type == RES_MEM_RESERVED)
107 entries[num_entries].type = E820_RESERVED;
111 hdr = get_next_hob(hdr);
114 /* Mark PCIe ECAM address range as reserved */
115 entries[num_entries].addr = CONFIG_PCIE_ECAM_BASE;
116 entries[num_entries].size = CONFIG_PCIE_ECAM_SIZE;
117 entries[num_entries].type = E820_RESERVED;
120 #ifdef CONFIG_HAVE_ACPI_RESUME
122 * Everything between U-Boot's stack and ram top needs to be
123 * reserved in order for ACPI S3 resume to work.
125 entries[num_entries].addr = gd->start_addr_sp - CONFIG_STACK_SIZE;
126 entries[num_entries].size = gd->ram_top - gd->start_addr_sp +
128 entries[num_entries].type = E820_RESERVED;
135 #if CONFIG_IS_ENABLED(HANDOFF) && IS_ENABLED(CONFIG_USE_HOB)
136 int handoff_arch_save(struct spl_handoff *ho)
138 ho->arch.usable_ram_top = fsp_get_usable_lowmem_top(gd->arch.hob_list);
139 ho->arch.hob_list = gd->arch.hob_list;