2 * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
4 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/acpi_s3.h>
12 #include <asm/cmos_layout.h>
13 #include <asm/early_cmos.h>
15 #include <asm/mrccache.h>
17 #include <asm/processor.h>
18 #include <asm/fsp/fsp_support.h>
20 DECLARE_GLOBAL_DATA_PTR;
27 int print_cpuinfo(void)
29 post_code(POST_CPU_INFO);
30 return default_print_cpuinfo();
33 int fsp_init_phase_pci(void)
37 /* call into FspNotify */
38 debug("Calling into FSP (notify phase INIT_PHASE_PCI): ");
39 status = fsp_notify(NULL, INIT_PHASE_PCI);
41 debug("fail, error code %x\n", status);
45 return status ? -EPERM : 0;
48 void board_final_cleanup(void)
52 /* call into FspNotify */
53 debug("Calling into FSP (notify phase INIT_PHASE_BOOT): ");
54 status = fsp_notify(NULL, INIT_PHASE_BOOT);
56 debug("fail, error code %x\n", status);
63 static __maybe_unused void *fsp_prepare_mrc_cache(void)
65 struct mrc_data_container *cache;
66 struct mrc_region entry;
69 ret = mrccache_get_region(NULL, &entry);
73 cache = mrccache_find_current(&entry);
77 debug("%s: mrc cache at %p, size %x checksum %04x\n", __func__,
78 cache->data, cache->data_size, cache->checksum);
83 #ifdef CONFIG_HAVE_ACPI_RESUME
84 int fsp_save_s3_stack(void)
89 if (gd->arch.prev_sleep_state == ACPI_S3)
92 ret = uclass_get_device(UCLASS_RTC, 0, &dev);
94 debug("Cannot find RTC: err=%d\n", ret);
98 /* Save the stack address to CMOS */
99 ret = rtc_write32(dev, CMOS_FSP_STACK_ADDR, gd->start_addr_sp);
101 debug("Save stack address to CMOS: err=%d\n", ret);
109 int arch_fsp_init(void)
112 int stack = CONFIG_FSP_TEMP_RAM_ADDR;
113 int boot_mode = BOOT_FULL_CONFIG;
114 #ifdef CONFIG_HAVE_ACPI_RESUME
115 int prev_sleep_state = chipset_prev_sleep_state();
116 gd->arch.prev_sleep_state = prev_sleep_state;
119 if (!gd->arch.hob_list) {
120 #ifdef CONFIG_ENABLE_MRC_CACHE
121 nvs = fsp_prepare_mrc_cache();
126 #ifdef CONFIG_HAVE_ACPI_RESUME
127 if (prev_sleep_state == ACPI_S3) {
129 /* If waking from S3 and no cache then */
130 debug("No MRC cache found in S3 resume path\n");
131 post_code(POST_RESUME_FAILURE);
132 /* Clear Sleep Type */
133 chipset_clear_sleep_state();
135 debug("Rebooting..\n");
137 /* Should not reach here.. */
138 panic("Reboot System");
142 * DM is not avaiable yet at this point, hence call
143 * CMOS access library which does not depend on DM.
145 stack = cmos_read32(CMOS_FSP_STACK_ADDR);
146 boot_mode = BOOT_ON_S3_RESUME;
150 * The first time we enter here, call fsp_init().
151 * Note the execution does not return to this function,
152 * instead it jumps to fsp_continue().
154 fsp_init(stack, boot_mode, nvs);
157 * The second time we enter here, adjust the size of malloc()
158 * pool before relocation. Given gd->malloc_base was adjusted
159 * after the call to board_init_f_init_reserve() in arch/x86/
160 * cpu/start.S, we should fix up gd->malloc_limit here.
162 gd->malloc_limit += CONFIG_FSP_SYS_MALLOC_F_LEN;