1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
10 #include <asm/acpi_s3.h>
11 #include <asm/cmos_layout.h>
12 #include <asm/early_cmos.h>
14 #include <asm/mrccache.h>
16 #include <asm/processor.h>
17 #include <asm/fsp/fsp_support.h>
19 DECLARE_GLOBAL_DATA_PTR;
26 int print_cpuinfo(void)
28 post_code(POST_CPU_INFO);
29 return default_print_cpuinfo();
32 int fsp_init_phase_pci(void)
36 /* call into FspNotify */
37 debug("Calling into FSP (notify phase INIT_PHASE_PCI): ");
38 status = fsp_notify(NULL, INIT_PHASE_PCI);
40 debug("fail, error code %x\n", status);
44 return status ? -EPERM : 0;
47 void board_final_cleanup(void)
51 /* call into FspNotify */
52 debug("Calling into FSP (notify phase INIT_PHASE_BOOT): ");
53 status = fsp_notify(NULL, INIT_PHASE_BOOT);
55 debug("fail, error code %x\n", status);
62 static __maybe_unused void *fsp_prepare_mrc_cache(void)
64 struct mrc_data_container *cache;
65 struct mrc_region entry;
68 ret = mrccache_get_region(NULL, &entry);
72 cache = mrccache_find_current(&entry);
76 debug("%s: mrc cache at %p, size %x checksum %04x\n", __func__,
77 cache->data, cache->data_size, cache->checksum);
82 #ifdef CONFIG_HAVE_ACPI_RESUME
83 int fsp_save_s3_stack(void)
88 if (gd->arch.prev_sleep_state == ACPI_S3)
91 ret = uclass_get_device(UCLASS_RTC, 0, &dev);
93 debug("Cannot find RTC: err=%d\n", ret);
97 /* Save the stack address to CMOS */
98 ret = rtc_write32(dev, CMOS_FSP_STACK_ADDR, gd->start_addr_sp);
100 debug("Save stack address to CMOS: err=%d\n", ret);
108 int arch_fsp_init(void)
111 int stack = CONFIG_FSP_TEMP_RAM_ADDR;
112 int boot_mode = BOOT_FULL_CONFIG;
113 #ifdef CONFIG_HAVE_ACPI_RESUME
114 int prev_sleep_state = chipset_prev_sleep_state();
115 gd->arch.prev_sleep_state = prev_sleep_state;
118 if (!gd->arch.hob_list) {
119 #ifdef CONFIG_ENABLE_MRC_CACHE
120 nvs = fsp_prepare_mrc_cache();
125 #ifdef CONFIG_HAVE_ACPI_RESUME
126 if (prev_sleep_state == ACPI_S3) {
128 /* If waking from S3 and no cache then */
129 debug("No MRC cache found in S3 resume path\n");
130 post_code(POST_RESUME_FAILURE);
131 /* Clear Sleep Type */
132 chipset_clear_sleep_state();
134 debug("Rebooting..\n");
135 outb(SYS_RST | RST_CPU, IO_PORT_RESET);
136 /* Should not reach here.. */
137 panic("Reboot System");
141 * DM is not available yet at this point, hence call
142 * CMOS access library which does not depend on DM.
144 stack = cmos_read32(CMOS_FSP_STACK_ADDR);
145 boot_mode = BOOT_ON_S3_RESUME;
149 * The first time we enter here, call fsp_init().
150 * Note the execution does not return to this function,
151 * instead it jumps to fsp_continue().
153 fsp_init(stack, boot_mode, nvs);
156 * The second time we enter here, adjust the size of malloc()
157 * pool before relocation. Given gd->malloc_base was adjusted
158 * after the call to board_init_f_init_reserve() in arch/x86/
159 * cpu/start.S, we should fix up gd->malloc_limit here.
161 gd->malloc_limit += CONFIG_FSP_SYS_MALLOC_F_LEN;