1 // SPDX-License-Identifier: GPL-2.0-only
3 * AMD CPU Microcode Update Driver for Linux
5 * This driver allows to upgrade microcode on F10h AMD
8 * Copyright (C) 2008-2011 Advanced Micro Devices Inc.
9 * 2013-2018 Borislav Petkov <bp@alien8.de>
11 * Author: Peter Oruba <peter.oruba@amd.com>
14 * Tigran Aivazian <aivazian.tigran@gmail.com>
17 * Copyright (C) 2013 Advanced Micro Devices, Inc.
19 * Author: Jacob Shin <jacob.shin@amd.com>
20 * Fixes: Borislav Petkov <bp@suse.de>
22 #define pr_fmt(fmt) "microcode: " fmt
24 #include <linux/earlycpio.h>
25 #include <linux/firmware.h>
26 #include <linux/uaccess.h>
27 #include <linux/vmalloc.h>
28 #include <linux/initrd.h>
29 #include <linux/kernel.h>
30 #include <linux/pci.h>
32 #include <asm/microcode_amd.h>
33 #include <asm/microcode.h>
34 #include <asm/processor.h>
35 #include <asm/setup.h>
39 static struct equiv_cpu_table {
40 unsigned int num_entries;
41 struct equiv_cpu_entry *entry;
45 * This points to the current valid container of microcode patches which we will
46 * save from the initrd/builtin before jettisoning its contents. @mc is the
47 * microcode patch we found to match.
50 struct microcode_amd *mc;
57 static u32 ucode_new_rev;
58 static u8 amd_ucode_patch[PATCH_MAX_SIZE];
61 * Microcode patch container file is prepended to the initrd in cpio
62 * format. See Documentation/x86/microcode.rst
65 ucode_path[] __maybe_unused = "/*(DEBLOBBED)*/";
67 static u16 find_equiv_id(struct equiv_cpu_table *et, u32 sig)
71 if (!et || !et->num_entries)
74 for (i = 0; i < et->num_entries; i++) {
75 struct equiv_cpu_entry *e = &et->entry[i];
77 if (sig == e->installed_cpu)
86 * Check whether there is a valid microcode container file at the beginning
87 * of @buf of size @buf_size. Set @early to use this function in the early path.
89 static bool verify_container(const u8 *buf, size_t buf_size, bool early)
93 if (buf_size <= CONTAINER_HDR_SZ) {
95 pr_debug("Truncated microcode container header.\n");
100 cont_magic = *(const u32 *)buf;
101 if (cont_magic != UCODE_MAGIC) {
103 pr_debug("Invalid magic value (0x%08x).\n", cont_magic);
112 * Check whether there is a valid, non-truncated CPU equivalence table at the
113 * beginning of @buf of size @buf_size. Set @early to use this function in the
116 static bool verify_equivalence_table(const u8 *buf, size_t buf_size, bool early)
118 const u32 *hdr = (const u32 *)buf;
119 u32 cont_type, equiv_tbl_len;
121 if (!verify_container(buf, buf_size, early))
125 if (cont_type != UCODE_EQUIV_CPU_TABLE_TYPE) {
127 pr_debug("Wrong microcode container equivalence table type: %u.\n",
133 buf_size -= CONTAINER_HDR_SZ;
135 equiv_tbl_len = hdr[2];
136 if (equiv_tbl_len < sizeof(struct equiv_cpu_entry) ||
137 buf_size < equiv_tbl_len) {
139 pr_debug("Truncated equivalence table.\n");
148 * Check whether there is a valid, non-truncated microcode patch section at the
149 * beginning of @buf of size @buf_size. Set @early to use this function in the
152 * On success, @sh_psize returns the patch size according to the section header,
156 __verify_patch_section(const u8 *buf, size_t buf_size, u32 *sh_psize, bool early)
161 if (buf_size < SECTION_HDR_SIZE) {
163 pr_debug("Truncated patch section.\n");
168 hdr = (const u32 *)buf;
172 if (p_type != UCODE_UCODE_TYPE) {
174 pr_debug("Invalid type field (0x%x) in container file section header.\n",
180 if (p_size < sizeof(struct microcode_header_amd)) {
182 pr_debug("Patch of size %u too short.\n", p_size);
193 * Check whether the passed remaining file @buf_size is large enough to contain
194 * a patch of the indicated @sh_psize (and also whether this size does not
195 * exceed the per-family maximum). @sh_psize is the size read from the section
198 static unsigned int __verify_patch_size(u8 family, u32 sh_psize, size_t buf_size)
203 return min_t(u32, sh_psize, buf_size);
205 #define F1XH_MPB_MAX_SIZE 2048
206 #define F14H_MPB_MAX_SIZE 1824
210 max_size = F1XH_MPB_MAX_SIZE;
213 max_size = F14H_MPB_MAX_SIZE;
216 WARN(1, "%s: WTF family: 0x%x\n", __func__, family);
221 if (sh_psize > min_t(u32, buf_size, max_size))
228 * Verify the patch in @buf.
232 * positive: patch is not for this family, skip it
236 verify_patch(u8 family, const u8 *buf, size_t buf_size, u32 *patch_size, bool early)
238 struct microcode_header_amd *mc_hdr;
244 if (!__verify_patch_section(buf, buf_size, &sh_psize, early))
248 * The section header length is not included in this indicated size
249 * but is present in the leftover file length so we need to subtract
250 * it before passing this value to the function below.
252 buf_size -= SECTION_HDR_SIZE;
255 * Check if the remaining buffer is big enough to contain a patch of
256 * size sh_psize, as the section claims.
258 if (buf_size < sh_psize) {
260 pr_debug("Patch of size %u truncated.\n", sh_psize);
265 ret = __verify_patch_size(family, sh_psize, buf_size);
268 pr_debug("Per-family patch size mismatch.\n");
272 *patch_size = sh_psize;
274 mc_hdr = (struct microcode_header_amd *)(buf + SECTION_HDR_SIZE);
275 if (mc_hdr->nb_dev_id || mc_hdr->sb_dev_id) {
277 pr_err("Patch-ID 0x%08x: chipset-specific code unsupported.\n", mc_hdr->patch_id);
281 proc_id = mc_hdr->processor_rev_id;
282 patch_fam = 0xf + (proc_id >> 12);
283 if (patch_fam != family)
290 * This scans the ucode blob for the proper container as we can have multiple
291 * containers glued together. Returns the equivalence ID from the equivalence
292 * table or 0 if none found.
293 * Returns the amount of bytes consumed while scanning. @desc contains all the
294 * data we're going to use in later stages of the application.
296 static size_t parse_container(u8 *ucode, size_t size, struct cont_desc *desc)
298 struct equiv_cpu_table table;
299 size_t orig_size = size;
300 u32 *hdr = (u32 *)ucode;
304 if (!verify_equivalence_table(ucode, size, true))
309 table.entry = (struct equiv_cpu_entry *)(buf + CONTAINER_HDR_SZ);
310 table.num_entries = hdr[2] / sizeof(struct equiv_cpu_entry);
313 * Find the equivalence ID of our CPU in this table. Even if this table
314 * doesn't contain a patch for the CPU, scan through the whole container
315 * so that it can be skipped in case there are other containers appended.
317 eq_id = find_equiv_id(&table, desc->cpuid_1_eax);
319 buf += hdr[2] + CONTAINER_HDR_SZ;
320 size -= hdr[2] + CONTAINER_HDR_SZ;
323 * Scan through the rest of the container to find where it ends. We do
324 * some basic sanity-checking too.
327 struct microcode_amd *mc;
331 ret = verify_patch(x86_family(desc->cpuid_1_eax), buf, size, &patch_size, true);
334 * Patch verification failed, skip to the next
335 * container, if there's one:
338 } else if (ret > 0) {
342 mc = (struct microcode_amd *)(buf + SECTION_HDR_SIZE);
343 if (eq_id == mc->hdr.processor_rev_id) {
344 desc->psize = patch_size;
349 /* Skip patch section header too: */
350 buf += patch_size + SECTION_HDR_SIZE;
351 size -= patch_size + SECTION_HDR_SIZE;
355 * If we have found a patch (desc->mc), it means we're looking at the
356 * container which has a patch for this CPU so return 0 to mean, @ucode
357 * already points to the proper container. Otherwise, we return the size
358 * we scanned so that we can advance to the next container in the
363 desc->size = orig_size - size;
369 return orig_size - size;
373 * Scan the ucode blob for the proper container as we can have multiple
374 * containers glued together.
376 static void scan_containers(u8 *ucode, size_t size, struct cont_desc *desc)
379 size_t s = parse_container(ucode, size, desc);
383 /* catch wraparound */
393 static int __apply_microcode_amd(struct microcode_amd *mc)
397 native_wrmsrl(MSR_AMD64_PATCH_LOADER, (u64)(long)&mc->hdr.data_code);
399 /* verify patch application was successful */
400 native_rdmsr(MSR_AMD64_PATCH_LEVEL, rev, dummy);
401 if (rev != mc->hdr.patch_id)
408 * Early load occurs before we can vmalloc(). So we look for the microcode
409 * patch container file in initrd, traverse equivalent cpu table, look for a
410 * matching microcode patch, and update, all in initrd memory in place.
411 * When vmalloc() is available for use later -- on 64-bit during first AP load,
412 * and on 32-bit during save_microcode_in_initrd_amd() -- we can call
413 * load_microcode_amd() to save equivalent cpu table and microcode patches in
414 * kernel heap memory.
416 * Returns true if container found (sets @desc), false otherwise.
419 apply_microcode_early_amd(u32 cpuid_1_eax, void *ucode, size_t size, bool save_patch)
421 struct cont_desc desc = { 0 };
422 u8 (*patch)[PATCH_MAX_SIZE];
423 struct microcode_amd *mc;
424 u32 rev, dummy, *new_rev;
428 new_rev = (u32 *)__pa_nodebug(&ucode_new_rev);
429 patch = (u8 (*)[PATCH_MAX_SIZE])__pa_nodebug(&amd_ucode_patch);
431 new_rev = &ucode_new_rev;
432 patch = &amd_ucode_patch;
435 desc.cpuid_1_eax = cpuid_1_eax;
437 scan_containers(ucode, size, &desc);
443 native_rdmsr(MSR_AMD64_PATCH_LEVEL, rev, dummy);
444 if (rev >= mc->hdr.patch_id)
447 if (!__apply_microcode_amd(mc)) {
448 *new_rev = mc->hdr.patch_id;
452 memcpy(patch, mc, min_t(u32, desc.psize, PATCH_MAX_SIZE));
458 static bool get_builtin_microcode(struct cpio_data *cp, unsigned int family)
461 char fw_name[36] = "/*(DEBLOBBED)*/";
464 snprintf(fw_name, sizeof(fw_name),
465 "/*(DEBLOBBED)*/", family);
467 return get_builtin_firmware(cp, fw_name);
473 static void __load_ucode_amd(unsigned int cpuid_1_eax, struct cpio_data *ret)
475 struct ucode_cpu_info *uci;
480 if (IS_ENABLED(CONFIG_X86_32)) {
481 uci = (struct ucode_cpu_info *)__pa_nodebug(ucode_cpu_info);
482 path = (const char *)__pa_nodebug(ucode_path);
485 uci = ucode_cpu_info;
490 if (!get_builtin_microcode(&cp, x86_family(cpuid_1_eax)))
491 cp = find_microcode_in_initrd(path, use_pa);
493 /* Needed in load_microcode_amd() */
494 uci->cpu_sig.sig = cpuid_1_eax;
499 void __init load_ucode_amd_bsp(unsigned int cpuid_1_eax)
501 struct cpio_data cp = { };
503 __load_ucode_amd(cpuid_1_eax, &cp);
504 if (!(cp.data && cp.size))
507 apply_microcode_early_amd(cpuid_1_eax, cp.data, cp.size, true);
510 void load_ucode_amd_ap(unsigned int cpuid_1_eax)
512 struct microcode_amd *mc;
514 u32 *new_rev, rev, dummy;
516 if (IS_ENABLED(CONFIG_X86_32)) {
517 mc = (struct microcode_amd *)__pa_nodebug(amd_ucode_patch);
518 new_rev = (u32 *)__pa_nodebug(&ucode_new_rev);
520 mc = (struct microcode_amd *)amd_ucode_patch;
521 new_rev = &ucode_new_rev;
524 native_rdmsr(MSR_AMD64_PATCH_LEVEL, rev, dummy);
526 /* Check whether we have saved a new patch already: */
527 if (*new_rev && rev < mc->hdr.patch_id) {
528 if (!__apply_microcode_amd(mc)) {
529 *new_rev = mc->hdr.patch_id;
534 __load_ucode_amd(cpuid_1_eax, &cp);
535 if (!(cp.data && cp.size))
538 apply_microcode_early_amd(cpuid_1_eax, cp.data, cp.size, false);
541 static enum ucode_state
542 load_microcode_amd(bool save, u8 family, const u8 *data, size_t size);
544 int __init save_microcode_in_initrd_amd(unsigned int cpuid_1_eax)
546 struct cont_desc desc = { 0 };
547 enum ucode_state ret;
550 cp = find_microcode_in_initrd(ucode_path, false);
551 if (!(cp.data && cp.size))
554 desc.cpuid_1_eax = cpuid_1_eax;
556 scan_containers(cp.data, cp.size, &desc);
560 ret = load_microcode_amd(true, x86_family(cpuid_1_eax), desc.data, desc.size);
561 if (ret > UCODE_UPDATED)
567 void reload_ucode_amd(void)
569 struct microcode_amd *mc;
572 mc = (struct microcode_amd *)amd_ucode_patch;
574 rdmsr(MSR_AMD64_PATCH_LEVEL, rev, dummy);
576 if (rev < mc->hdr.patch_id) {
577 if (!__apply_microcode_amd(mc)) {
578 ucode_new_rev = mc->hdr.patch_id;
579 pr_info("reload patch_level=0x%08x\n", ucode_new_rev);
583 static u16 __find_equiv_id(unsigned int cpu)
585 struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
586 return find_equiv_id(&equiv_table, uci->cpu_sig.sig);
590 * a small, trivial cache of per-family ucode patches
592 static struct ucode_patch *cache_find_patch(u16 equiv_cpu)
594 struct ucode_patch *p;
596 list_for_each_entry(p, µcode_cache, plist)
597 if (p->equiv_cpu == equiv_cpu)
602 static void update_cache(struct ucode_patch *new_patch)
604 struct ucode_patch *p;
606 list_for_each_entry(p, µcode_cache, plist) {
607 if (p->equiv_cpu == new_patch->equiv_cpu) {
608 if (p->patch_id >= new_patch->patch_id) {
609 /* we already have the latest patch */
610 kfree(new_patch->data);
615 list_replace(&p->plist, &new_patch->plist);
621 /* no patch found, add it */
622 list_add_tail(&new_patch->plist, µcode_cache);
625 static void free_cache(void)
627 struct ucode_patch *p, *tmp;
629 list_for_each_entry_safe(p, tmp, µcode_cache, plist) {
630 __list_del(p->plist.prev, p->plist.next);
636 static struct ucode_patch *find_patch(unsigned int cpu)
640 equiv_id = __find_equiv_id(cpu);
644 return cache_find_patch(equiv_id);
647 static int collect_cpu_info_amd(int cpu, struct cpu_signature *csig)
649 struct cpuinfo_x86 *c = &cpu_data(cpu);
650 struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
651 struct ucode_patch *p;
653 csig->sig = cpuid_eax(0x00000001);
654 csig->rev = c->microcode;
657 * a patch could have been loaded early, set uci->mc so that
658 * mc_bp_resume() can call apply_microcode()
661 if (p && (p->patch_id == csig->rev))
664 pr_info("CPU%d: patch_level=0x%08x\n", cpu, csig->rev);
669 static enum ucode_state apply_microcode_amd(int cpu)
671 struct cpuinfo_x86 *c = &cpu_data(cpu);
672 struct microcode_amd *mc_amd;
673 struct ucode_cpu_info *uci;
674 struct ucode_patch *p;
675 enum ucode_state ret;
678 BUG_ON(raw_smp_processor_id() != cpu);
680 uci = ucode_cpu_info + cpu;
689 rdmsr(MSR_AMD64_PATCH_LEVEL, rev, dummy);
691 /* need to apply patch? */
692 if (rev >= mc_amd->hdr.patch_id) {
697 if (__apply_microcode_amd(mc_amd)) {
698 pr_err("CPU%d: update failed for patch_level=0x%08x\n",
699 cpu, mc_amd->hdr.patch_id);
703 rev = mc_amd->hdr.patch_id;
706 pr_info("CPU%d: new patch_level=0x%08x\n", cpu, rev);
709 uci->cpu_sig.rev = rev;
712 /* Update boot_cpu_data's revision too, if we're on the BSP: */
713 if (c->cpu_index == boot_cpu_data.cpu_index)
714 boot_cpu_data.microcode = rev;
719 static size_t install_equiv_cpu_table(const u8 *buf, size_t buf_size)
724 if (!verify_equivalence_table(buf, buf_size, false))
727 hdr = (const u32 *)buf;
728 equiv_tbl_len = hdr[2];
730 equiv_table.entry = vmalloc(equiv_tbl_len);
731 if (!equiv_table.entry) {
732 pr_err("failed to allocate equivalent CPU table\n");
736 memcpy(equiv_table.entry, buf + CONTAINER_HDR_SZ, equiv_tbl_len);
737 equiv_table.num_entries = equiv_tbl_len / sizeof(struct equiv_cpu_entry);
739 /* add header length */
740 return equiv_tbl_len + CONTAINER_HDR_SZ;
743 static void free_equiv_cpu_table(void)
745 vfree(equiv_table.entry);
746 memset(&equiv_table, 0, sizeof(equiv_table));
749 static void cleanup(void)
751 free_equiv_cpu_table();
756 * Return a non-negative value even if some of the checks failed so that
757 * we can skip over the next patch. If we return a negative value, we
758 * signal a grave error like a memory allocation has failed and the
759 * driver cannot continue functioning normally. In such cases, we tear
760 * down everything we've used up so far and exit.
762 static int verify_and_add_patch(u8 family, u8 *fw, unsigned int leftover,
763 unsigned int *patch_size)
765 struct microcode_header_amd *mc_hdr;
766 struct ucode_patch *patch;
770 ret = verify_patch(family, fw, leftover, patch_size, false);
774 patch = kzalloc(sizeof(*patch), GFP_KERNEL);
776 pr_err("Patch allocation failure.\n");
780 patch->data = kmemdup(fw + SECTION_HDR_SIZE, *patch_size, GFP_KERNEL);
782 pr_err("Patch data allocation failure.\n");
787 mc_hdr = (struct microcode_header_amd *)(fw + SECTION_HDR_SIZE);
788 proc_id = mc_hdr->processor_rev_id;
790 INIT_LIST_HEAD(&patch->plist);
791 patch->patch_id = mc_hdr->patch_id;
792 patch->equiv_cpu = proc_id;
794 pr_debug("%s: Added patch_id: 0x%08x, proc_id: 0x%04x\n",
795 __func__, patch->patch_id, proc_id);
797 /* ... and add to cache. */
803 static enum ucode_state __load_microcode_amd(u8 family, const u8 *data,
809 offset = install_equiv_cpu_table(data, size);
816 if (*(u32 *)fw != UCODE_UCODE_TYPE) {
817 pr_err("invalid type field in container file section header\n");
818 free_equiv_cpu_table();
823 unsigned int crnt_size = 0;
826 ret = verify_and_add_patch(family, fw, size, &crnt_size);
830 fw += crnt_size + SECTION_HDR_SIZE;
831 size -= (crnt_size + SECTION_HDR_SIZE);
837 static enum ucode_state
838 load_microcode_amd(bool save, u8 family, const u8 *data, size_t size)
840 struct ucode_patch *p;
841 enum ucode_state ret;
843 /* free old equiv table */
844 free_equiv_cpu_table();
846 ret = __load_microcode_amd(family, data, size);
847 if (ret != UCODE_OK) {
856 if (boot_cpu_data.microcode >= p->patch_id)
862 /* save BSP's matching patch for early load */
866 memset(amd_ucode_patch, 0, PATCH_MAX_SIZE);
867 memcpy(amd_ucode_patch, p->data, min_t(u32, ksize(p->data), PATCH_MAX_SIZE));
873 static enum ucode_state request_microcode_amd(int cpu, struct device *device,
876 char fw_name[36] = "/*(DEBLOBBED)*/";
877 struct cpuinfo_x86 *c = &cpu_data(cpu);
878 bool bsp = c->cpu_index == boot_cpu_data.cpu_index;
879 enum ucode_state ret = UCODE_NFOUND;
880 const struct firmware *fw;
882 /* reload ucode container only on the boot cpu */
883 if (!refresh_fw || !bsp)
887 snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", c->x86);
889 if (reject_firmware_direct(&fw, (const char *)fw_name, device)) {
890 pr_debug("failed to load file %s\n", fw_name);
895 if (!verify_container(fw->data, fw->size, false))
898 ret = load_microcode_amd(bsp, c->x86, fw->data, fw->size);
901 release_firmware(fw);
907 static enum ucode_state
908 request_microcode_user(int cpu, const void __user *buf, size_t size)
913 static void microcode_fini_cpu_amd(int cpu)
915 struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
920 static struct microcode_ops microcode_amd_ops = {
921 .request_microcode_user = request_microcode_user,
922 .request_microcode_fw = request_microcode_amd,
923 .collect_cpu_info = collect_cpu_info_amd,
924 .apply_microcode = apply_microcode_amd,
925 .microcode_fini_cpu = microcode_fini_cpu_amd,
928 struct microcode_ops * __init init_amd_microcode(void)
930 struct cpuinfo_x86 *c = &boot_cpu_data;
932 if (c->x86_vendor != X86_VENDOR_AMD || c->x86 < 0x10) {
933 pr_warn("AMD CPU family 0x%x not supported\n", c->x86);
938 pr_info_once("microcode updated early to new patch_level=0x%08x\n",
941 return µcode_amd_ops;
944 void __exit exit_amd_microcode(void)