1 // SPDX-License-Identifier: GPL-2.0
3 #include <linux/sched.h>
4 #include <linux/sched/clock.h>
6 #include <asm/cpufeature.h>
7 #include <asm/e820/api.h>
13 #define ACE_PRESENT (1 << 6)
14 #define ACE_ENABLED (1 << 7)
15 #define ACE_FCR (1 << 28) /* MSR_VIA_FCR */
17 #define RNG_PRESENT (1 << 2)
18 #define RNG_ENABLED (1 << 3)
19 #define RNG_ENABLE (1 << 6) /* MSR_VIA_RNG */
21 static void init_c3(struct cpuinfo_x86 *c)
25 /* Test for Centaur Extended Feature Flags presence */
26 if (cpuid_eax(0xC0000000) >= 0xC0000001) {
27 u32 tmp = cpuid_edx(0xC0000001);
29 /* enable ACE unit, if present and disabled */
30 if ((tmp & (ACE_PRESENT | ACE_ENABLED)) == ACE_PRESENT) {
31 rdmsr(MSR_VIA_FCR, lo, hi);
32 lo |= ACE_FCR; /* enable ACE unit */
33 wrmsr(MSR_VIA_FCR, lo, hi);
34 pr_info("CPU: Enabled ACE h/w crypto\n");
37 /* enable RNG unit, if present and disabled */
38 if ((tmp & (RNG_PRESENT | RNG_ENABLED)) == RNG_PRESENT) {
39 rdmsr(MSR_VIA_RNG, lo, hi);
40 lo |= RNG_ENABLE; /* enable RNG unit */
41 wrmsr(MSR_VIA_RNG, lo, hi);
42 pr_info("CPU: Enabled h/w RNG\n");
45 /* store Centaur Extended Feature Flags as
46 * word 5 of the CPU capability bit array
48 c->x86_capability[CPUID_C000_0001_EDX] = cpuid_edx(0xC0000001);
51 /* Cyrix III family needs CX8 & PGE explicitly enabled. */
52 if (c->x86_model >= 6 && c->x86_model <= 13) {
53 rdmsr(MSR_VIA_FCR, lo, hi);
55 wrmsr(MSR_VIA_FCR, lo, hi);
56 set_cpu_cap(c, X86_FEATURE_CX8);
59 /* Before Nehemiah, the C3's had 3dNOW! */
60 if (c->x86_model >= 6 && c->x86_model < 9)
61 set_cpu_cap(c, X86_FEATURE_3DNOW);
63 if (c->x86 == 0x6 && c->x86_model >= 0xf) {
64 c->x86_cache_alignment = c->x86_clflush_size * 2;
65 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
90 static void early_init_centaur(struct cpuinfo_x86 *c)
95 /* Emulate MTRRs using Centaur's MCR. */
96 set_cpu_cap(c, X86_FEATURE_CENTAUR_MCR);
100 if (c->x86_model >= 0xf)
101 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
105 set_cpu_cap(c, X86_FEATURE_SYSENTER32);
107 if (c->x86_power & (1 << 8)) {
108 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
109 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
113 static void init_centaur(struct cpuinfo_x86 *c)
123 * Bit 31 in normal CPUID used for nonstandard 3DNow ID;
124 * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway
126 clear_cpu_cap(c, 0*32+31);
128 early_init_centaur(c);
129 init_intel_cacheinfo(c);
130 detect_num_cpu_cores(c);
135 if (c->cpuid_level > 9) {
136 unsigned int eax = cpuid_eax(10);
139 * Check for version and the number of counters
140 * Version(eax[7:0]) can't be 0;
141 * Counters(eax[15:8]) should be greater than 1;
143 if ((eax & 0xff) && (((eax >> 8) & 0xff) > 1))
144 set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON);
150 switch (c->x86_model) {
153 fcr_set = ECX8|DSMC|EDCTLB|EMMX|ERETSTK;
155 pr_notice("Disabling bugged TSC.\n");
156 clear_cpu_cap(c, X86_FEATURE_TSC);
159 switch (c->x86_stepping) {
170 fcr_set = ECX8|DSMC|DTLOCK|EMMX|EBRPRED|ERETSTK|
176 fcr_set = ECX8|DSMC|DTLOCK|EMMX|EBRPRED|ERETSTK|
184 rdmsr(MSR_IDT_FCR1, lo, hi);
185 newlo = (lo|fcr_set) & (~fcr_clr);
188 pr_info("Centaur FCR was 0x%X now 0x%X\n",
190 wrmsr(MSR_IDT_FCR1, newlo, hi);
192 pr_info("Centaur FCR is 0x%X\n", lo);
194 /* Emulate MTRRs using Centaur's MCR. */
195 set_cpu_cap(c, X86_FEATURE_CENTAUR_MCR);
197 set_cpu_cap(c, X86_FEATURE_CX8);
198 /* Set 3DNow! on Winchip 2 and above. */
199 if (c->x86_model >= 8)
200 set_cpu_cap(c, X86_FEATURE_3DNOW);
201 /* See if we can find out some more. */
202 if (cpuid_eax(0x80000000) >= 0x80000005) {
204 cpuid(0x80000005, &aa, &bb, &cc, &dd);
205 /* Add L1 data and code cache sizes. */
206 c->x86_cache_size = (cc>>24)+(dd>>24);
208 sprintf(c->x86_model_id, "WinChip %s", name);
216 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
219 init_ia32_feat_ctl(c);
224 centaur_size_cache(struct cpuinfo_x86 *c, unsigned int size)
226 /* VIA C3 CPUs (670-68F) need further shifting. */
227 if ((c->x86 == 6) && ((c->x86_model == 7) || (c->x86_model == 8)))
231 * There's also an erratum in Nehemiah stepping 1, which
232 * returns '65KB' instead of '64KB'
233 * - Note, it seems this may only be in engineering samples.
235 if ((c->x86 == 6) && (c->x86_model == 9) &&
236 (c->x86_stepping == 1) && (size == 65))
242 static const struct cpu_dev centaur_cpu_dev = {
243 .c_vendor = "Centaur",
244 .c_ident = { "CentaurHauls" },
245 .c_early_init = early_init_centaur,
246 .c_init = init_centaur,
248 .legacy_cache_size = centaur_size_cache,
250 .c_x86_vendor = X86_VENDOR_CENTAUR,
253 cpu_dev_register(centaur_cpu_dev);