arch/x86/kernel/cpu/bugs.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  *  Copyright (C) 1994  Linus Torvalds
   4  *
   5  *  Cyrix stuff, June 1998 by:
   6  *      - Rafael R. Reilova (moved everything from head.S),
   7  *        <rreilova@ececs.uc.edu>
   8  *      - Channing Corn (tests & fixes),
   9  *      - Andrew D. Balsa (code cleanup).
  10  */
  11 #include <linux/init.h>
  12 #include <linux/utsname.h>
  13 #include <linux/cpu.h>
  14 #include <linux/module.h>
  15 #include <linux/nospec.h>
  16 #include <linux/prctl.h>
  17 #include <linux/sched/smt.h>
  18
  19 #include <asm/spec-ctrl.h>
  20 #include <asm/cmdline.h>
  21 #include <asm/bugs.h>
  22 #include <asm/processor.h>
  23 #include <asm/processor-flags.h>
  24 #include <asm/fpu/internal.h>
  25 #include <asm/msr.h>
  26 #include <asm/vmx.h>
  27 #include <asm/paravirt.h>
  28 #include <asm/alternative.h>
  29 #include <asm/pgtable.h>
  30 #include <asm/set_memory.h>
  31 #include <asm/intel-family.h>
  32 #include <asm/e820/api.h>
  33 #include <asm/hypervisor.h>
  34
  35 #include "cpu.h"
  36
  37 static void __init spectre_v1_select_mitigation(void);
  38 static void __init spectre_v2_select_mitigation(void);
  39 static void __init ssb_select_mitigation(void);
  40 static void __init l1tf_select_mitigation(void);
  41 static void __init mds_select_mitigation(void);
  42 static void __init mds_print_mitigation(void);
  43 static void __init taa_select_mitigation(void);
  44 static void __init srbds_select_mitigation(void);
  45
  46 /* The base value of the SPEC_CTRL MSR that always has to be preserved. */
  47 u64 x86_spec_ctrl_base;
  48 EXPORT_SYMBOL_GPL(x86_spec_ctrl_base);
  49 static DEFINE_MUTEX(spec_ctrl_mutex);
  50
  51 /*
  52  * The vendor and possibly platform specific bits which can be modified in
  53  * x86_spec_ctrl_base.
  54  */
  55 static u64 __ro_after_init x86_spec_ctrl_mask = SPEC_CTRL_IBRS;
  56
  57 /*
  58  * AMD specific MSR info for Speculative Store Bypass control.
  59  * x86_amd_ls_cfg_ssbd_mask is initialized in identify_boot_cpu().
  60  */
  61 u64 __ro_after_init x86_amd_ls_cfg_base;
  62 u64 __ro_after_init x86_amd_ls_cfg_ssbd_mask;
  63
  64 /* Control conditional STIBP in switch_to() */
  65 DEFINE_STATIC_KEY_FALSE(switch_to_cond_stibp);
  66 /* Control conditional IBPB in switch_mm() */
  67 DEFINE_STATIC_KEY_FALSE(switch_mm_cond_ibpb);
  68 /* Control unconditional IBPB in switch_mm() */
  69 DEFINE_STATIC_KEY_FALSE(switch_mm_always_ibpb);
  70
  71 /* Control MDS CPU buffer clear before returning to user space */
  72 DEFINE_STATIC_KEY_FALSE(mds_user_clear);
  73 EXPORT_SYMBOL_GPL(mds_user_clear);
  74 /* Control MDS CPU buffer clear before idling (halt, mwait) */
  75 DEFINE_STATIC_KEY_FALSE(mds_idle_clear);
  76 EXPORT_SYMBOL_GPL(mds_idle_clear);
  77
  78 void __init check_bugs(void)
  79 {
  80         identify_boot_cpu();
  81
  82         /*
  83          * identify_boot_cpu() initialized SMT support information, let the
  84          * core code know.
  85          */
  86         cpu_smt_check_topology();
  87
  88         if (!IS_ENABLED(CONFIG_SMP)) {
  89                 pr_info("CPU: ");
  90                 print_cpu_info(&boot_cpu_data);
  91         }
  92
  93         /*
  94          * Read the SPEC_CTRL MSR to account for reserved bits which may
  95          * have unknown values. AMD64_LS_CFG MSR is cached in the early AMD
  96          * init code as it is not enumerated and depends on the family.
  97          */
  98         if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL))
  99                 rdmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
 100
 101         /* Allow STIBP in MSR_SPEC_CTRL if supported */
 102         if (boot_cpu_has(X86_FEATURE_STIBP))
 103                 x86_spec_ctrl_mask |= SPEC_CTRL_STIBP;
 104
 105         /* Select the proper CPU mitigations before patching alternatives: */
 106         spectre_v1_select_mitigation();
 107         spectre_v2_select_mitigation();
 108         ssb_select_mitigation();
 109         l1tf_select_mitigation();
 110         mds_select_mitigation();
 111         taa_select_mitigation();
 112         srbds_select_mitigation();
 113
 114         /*
 115          * As MDS and TAA mitigations are inter-related, print MDS
 116          * mitigation until after TAA mitigation selection is done.
 117          */
 118         mds_print_mitigation();
 119
 120         arch_smt_update();
 121
 122 #ifdef CONFIG_X86_32
 123         /*
 124          * Check whether we are able to run this kernel safely on SMP.
 125          *
 126          * - i386 is no longer supported.
 127          * - In order to run on anything without a TSC, we need to be
 128          *   compiled for a i486.
 129          */
 130         if (boot_cpu_data.x86 < 4)
 131                 panic("Kernel requires i486+ for 'invlpg' and other features");
 132
 133         init_utsname()->machine[1] =
 134                 '0' + (boot_cpu_data.x86 > 6 ? 6 : boot_cpu_data.x86);
 135         alternative_instructions();
 136
 137         fpu__init_check_bugs();
 138 #else /* CONFIG_X86_64 */
 139         alternative_instructions();
 140
 141         /*
 142          * Make sure the first 2MB area is not mapped by huge pages
 143          * There are typically fixed size MTRRs in there and overlapping
 144          * MTRRs into large pages causes slow downs.
 145          *
 146          * Right now we don't do that with gbpages because there seems
 147          * very little benefit for that case.
 148          */
 149         if (!direct_gbpages)
 150                 set_memory_4k((unsigned long)__va(0), 1);
 151 #endif
 152 }
 153
 154 void
 155 x86_virt_spec_ctrl(u64 guest_spec_ctrl, u64 guest_virt_spec_ctrl, bool setguest)
 156 {
 157         u64 msrval, guestval, hostval = x86_spec_ctrl_base;
 158         struct thread_info *ti = current_thread_info();
 159
 160         /* Is MSR_SPEC_CTRL implemented ? */
 161         if (static_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) {
 162                 /*
 163                  * Restrict guest_spec_ctrl to supported values. Clear the
 164                  * modifiable bits in the host base value and or the
 165                  * modifiable bits from the guest value.
 166                  */
 167                 guestval = hostval & ~x86_spec_ctrl_mask;
 168                 guestval |= guest_spec_ctrl & x86_spec_ctrl_mask;
 169
 170                 /* SSBD controlled in MSR_SPEC_CTRL */
 171                 if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) ||
 172                     static_cpu_has(X86_FEATURE_AMD_SSBD))
 173                         hostval |= ssbd_tif_to_spec_ctrl(ti->flags);
 174
 175                 /* Conditional STIBP enabled? */
 176                 if (static_branch_unlikely(&switch_to_cond_stibp))
 177                         hostval |= stibp_tif_to_spec_ctrl(ti->flags);
 178
 179                 if (hostval != guestval) {
 180                         msrval = setguest ? guestval : hostval;
 181                         wrmsrl(MSR_IA32_SPEC_CTRL, msrval);
 182                 }
 183         }
 184
 185         /*
 186          * If SSBD is not handled in MSR_SPEC_CTRL on AMD, update
 187          * MSR_AMD64_L2_CFG or MSR_VIRT_SPEC_CTRL if supported.
 188          */
 189         if (!static_cpu_has(X86_FEATURE_LS_CFG_SSBD) &&
 190             !static_cpu_has(X86_FEATURE_VIRT_SSBD))
 191                 return;
 192
 193         /*
 194          * If the host has SSBD mitigation enabled, force it in the host's
 195          * virtual MSR value. If its not permanently enabled, evaluate
 196          * current's TIF_SSBD thread flag.
 197          */
 198         if (static_cpu_has(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE))
 199                 hostval = SPEC_CTRL_SSBD;
 200         else
 201                 hostval = ssbd_tif_to_spec_ctrl(ti->flags);
 202
 203         /* Sanitize the guest value */
 204         guestval = guest_virt_spec_ctrl & SPEC_CTRL_SSBD;
 205
 206         if (hostval != guestval) {
 207                 unsigned long tif;
 208
 209                 tif = setguest ? ssbd_spec_ctrl_to_tif(guestval) :
 210                                  ssbd_spec_ctrl_to_tif(hostval);
 211
 212                 speculation_ctrl_update(tif);
 213         }
 214 }
 215 EXPORT_SYMBOL_GPL(x86_virt_spec_ctrl);
 216
 217 static void x86_amd_ssb_disable(void)
 218 {
 219         u64 msrval = x86_amd_ls_cfg_base | x86_amd_ls_cfg_ssbd_mask;
 220
 221         if (boot_cpu_has(X86_FEATURE_VIRT_SSBD))
 222                 wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL, SPEC_CTRL_SSBD);
 223         else if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD))
 224                 wrmsrl(MSR_AMD64_LS_CFG, msrval);
 225 }
 226
 227 #undef pr_fmt
 228 #define pr_fmt(fmt)     "MDS: " fmt
 229
 230 /* Default mitigation for MDS-affected CPUs */
 231 static enum mds_mitigations mds_mitigation __ro_after_init = MDS_MITIGATION_FULL;
 232 static bool mds_nosmt __ro_after_init = false;
 233
 234 static const char * const mds_strings[] = {
 235         [MDS_MITIGATION_OFF]    = "Vulnerable",
 236         [MDS_MITIGATION_FULL]   = "Mitigation: Clear CPU buffers",
 237         [MDS_MITIGATION_VMWERV] = "Vulnerable: Clear CPU buffers attempted, no microcode",
 238 };
 239
 240 static void __init mds_select_mitigation(void)
 241 {
 242         if (!boot_cpu_has_bug(X86_BUG_MDS) || cpu_mitigations_off()) {
 243                 mds_mitigation = MDS_MITIGATION_OFF;
 244                 return;
 245         }
 246
 247         if (mds_mitigation == MDS_MITIGATION_FULL) {
 248                 if (!boot_cpu_has(X86_FEATURE_MD_CLEAR))
 249                         mds_mitigation = MDS_MITIGATION_VMWERV;
 250
 251                 static_branch_enable(&mds_user_clear);
 252
 253                 if (!boot_cpu_has(X86_BUG_MSBDS_ONLY) &&
 254                     (mds_nosmt || cpu_mitigations_auto_nosmt()))
 255                         cpu_smt_disable(false);
 256         }
 257 }
 258
 259 static void __init mds_print_mitigation(void)
 260 {
 261         if (!boot_cpu_has_bug(X86_BUG_MDS) || cpu_mitigations_off())
 262                 return;
 263
 264         pr_info("%s\n", mds_strings[mds_mitigation]);
 265 }
 266
 267 static int __init mds_cmdline(char *str)
 268 {
 269         if (!boot_cpu_has_bug(X86_BUG_MDS))
 270                 return 0;
 271
 272         if (!str)
 273                 return -EINVAL;
 274
 275         if (!strcmp(str, "off"))
 276                 mds_mitigation = MDS_MITIGATION_OFF;
 277         else if (!strcmp(str, "full"))
 278                 mds_mitigation = MDS_MITIGATION_FULL;
 279         else if (!strcmp(str, "full,nosmt")) {
 280                 mds_mitigation = MDS_MITIGATION_FULL;
 281                 mds_nosmt = true;
 282         }
 283
 284         return 0;
 285 }
 286 early_param("mds", mds_cmdline);
 287
 288 #undef pr_fmt
 289 #define pr_fmt(fmt)     "TAA: " fmt
 290
 291 enum taa_mitigations {
 292         TAA_MITIGATION_OFF,
 293         TAA_MITIGATION_UCODE_NEEDED,
 294         TAA_MITIGATION_VERW,
 295         TAA_MITIGATION_TSX_DISABLED,
 296 };
 297
 298 /* Default mitigation for TAA-affected CPUs */
 299 static enum taa_mitigations taa_mitigation __ro_after_init = TAA_MITIGATION_VERW;
 300 static bool taa_nosmt __ro_after_init;
 301
 302 static const char * const taa_strings[] = {
 303         [TAA_MITIGATION_OFF]            = "Vulnerable",
 304         [TAA_MITIGATION_UCODE_NEEDED]   = "Vulnerable: Clear CPU buffers attempted, no microcode",
 305         [TAA_MITIGATION_VERW]           = "Mitigation: Clear CPU buffers",
 306         [TAA_MITIGATION_TSX_DISABLED]   = "Mitigation: TSX disabled",
 307 };
 308
 309 static void __init taa_select_mitigation(void)
 310 {
 311         u64 ia32_cap;
 312
 313         if (!boot_cpu_has_bug(X86_BUG_TAA)) {
 314                 taa_mitigation = TAA_MITIGATION_OFF;
 315                 return;
 316         }
 317
 318         /* TSX previously disabled by tsx=off */
 319         if (!boot_cpu_has(X86_FEATURE_RTM)) {
 320                 taa_mitigation = TAA_MITIGATION_TSX_DISABLED;
 321                 goto out;
 322         }
 323
 324         if (cpu_mitigations_off()) {
 325                 taa_mitigation = TAA_MITIGATION_OFF;
 326                 return;
 327         }
 328
 329         /*
 330          * TAA mitigation via VERW is turned off if both
 331          * tsx_async_abort=off and mds=off are specified.
 332          */
 333         if (taa_mitigation == TAA_MITIGATION_OFF &&
 334             mds_mitigation == MDS_MITIGATION_OFF)
 335                 goto out;
 336
 337         if (boot_cpu_has(X86_FEATURE_MD_CLEAR))
 338                 taa_mitigation = TAA_MITIGATION_VERW;
 339         else
 340                 taa_mitigation = TAA_MITIGATION_UCODE_NEEDED;
 341
 342         /*
 343          * VERW doesn't clear the CPU buffers when MD_CLEAR=1 and MDS_NO=1.
 344          * A microcode update fixes this behavior to clear CPU buffers. It also
 345          * adds support for MSR_IA32_TSX_CTRL which is enumerated by the
 346          * ARCH_CAP_TSX_CTRL_MSR bit.
 347          *
 348          * On MDS_NO=1 CPUs if ARCH_CAP_TSX_CTRL_MSR is not set, microcode
 349          * update is required.
 350          */
 351         ia32_cap = x86_read_arch_cap_msr();
 352         if ( (ia32_cap & ARCH_CAP_MDS_NO) &&
 353             !(ia32_cap & ARCH_CAP_TSX_CTRL_MSR))
 354                 taa_mitigation = TAA_MITIGATION_UCODE_NEEDED;
 355
 356         /*
 357          * TSX is enabled, select alternate mitigation for TAA which is
 358          * the same as MDS. Enable MDS static branch to clear CPU buffers.
 359          *
 360          * For guests that can't determine whether the correct microcode is
 361          * present on host, enable the mitigation for UCODE_NEEDED as well.
 362          */
 363         static_branch_enable(&mds_user_clear);
 364
 365         if (taa_nosmt || cpu_mitigations_auto_nosmt())
 366                 cpu_smt_disable(false);
 367
 368         /*
 369          * Update MDS mitigation, if necessary, as the mds_user_clear is
 370          * now enabled for TAA mitigation.
 371          */
 372         if (mds_mitigation == MDS_MITIGATION_OFF &&
 373             boot_cpu_has_bug(X86_BUG_MDS)) {
 374                 mds_mitigation = MDS_MITIGATION_FULL;
 375                 mds_select_mitigation();
 376         }
 377 out:
 378         pr_info("%s\n", taa_strings[taa_mitigation]);
 379 }
 380
 381 static int __init tsx_async_abort_parse_cmdline(char *str)
 382 {
 383         if (!boot_cpu_has_bug(X86_BUG_TAA))
 384                 return 0;
 385
 386         if (!str)
 387                 return -EINVAL;
 388
 389         if (!strcmp(str, "off")) {
 390                 taa_mitigation = TAA_MITIGATION_OFF;
 391         } else if (!strcmp(str, "full")) {
 392                 taa_mitigation = TAA_MITIGATION_VERW;
 393         } else if (!strcmp(str, "full,nosmt")) {
 394                 taa_mitigation = TAA_MITIGATION_VERW;
 395                 taa_nosmt = true;
 396         }
 397
 398         return 0;
 399 }
 400 early_param("tsx_async_abort", tsx_async_abort_parse_cmdline);
 401
 402 #undef pr_fmt
 403 #define pr_fmt(fmt)     "SRBDS: " fmt
 404
 405 enum srbds_mitigations {
 406         SRBDS_MITIGATION_OFF,
 407         SRBDS_MITIGATION_UCODE_NEEDED,
 408         SRBDS_MITIGATION_FULL,
 409         SRBDS_MITIGATION_TSX_OFF,
 410         SRBDS_MITIGATION_HYPERVISOR,
 411 };
 412
 413 static enum srbds_mitigations srbds_mitigation __ro_after_init = SRBDS_MITIGATION_FULL;
 414
 415 static const char * const srbds_strings[] = {
 416         [SRBDS_MITIGATION_OFF]          = "Vulnerable",
 417         [SRBDS_MITIGATION_UCODE_NEEDED] = "Vulnerable: No microcode",
 418         [SRBDS_MITIGATION_FULL]         = "Mitigation: Microcode",
 419         [SRBDS_MITIGATION_TSX_OFF]      = "Mitigation: TSX disabled",
 420         [SRBDS_MITIGATION_HYPERVISOR]   = "Unknown: Dependent on hypervisor status",
 421 };
 422
 423 static bool srbds_off;
 424
 425 void update_srbds_msr(void)
 426 {
 427         u64 mcu_ctrl;
 428
 429         if (!boot_cpu_has_bug(X86_BUG_SRBDS))
 430                 return;
 431
 432         if (boot_cpu_has(X86_FEATURE_HYPERVISOR))
 433                 return;
 434
 435         if (srbds_mitigation == SRBDS_MITIGATION_UCODE_NEEDED)
 436                 return;
 437
 438         rdmsrl(MSR_IA32_MCU_OPT_CTRL, mcu_ctrl);
 439
 440         switch (srbds_mitigation) {
 441         case SRBDS_MITIGATION_OFF:
 442         case SRBDS_MITIGATION_TSX_OFF:
 443                 mcu_ctrl |= RNGDS_MITG_DIS;
 444                 break;
 445         case SRBDS_MITIGATION_FULL:
 446                 mcu_ctrl &= ~RNGDS_MITG_DIS;
 447                 break;
 448         default:
 449                 break;
 450         }
 451
 452         wrmsrl(MSR_IA32_MCU_OPT_CTRL, mcu_ctrl);
 453 }
 454
 455 static void __init srbds_select_mitigation(void)
 456 {
 457         u64 ia32_cap;
 458
 459         if (!boot_cpu_has_bug(X86_BUG_SRBDS))
 460                 return;
 461
 462         /*
 463          * Check to see if this is one of the MDS_NO systems supporting
 464          * TSX that are only exposed to SRBDS when TSX is enabled.
 465          */
 466         ia32_cap = x86_read_arch_cap_msr();
 467         if ((ia32_cap & ARCH_CAP_MDS_NO) && !boot_cpu_has(X86_FEATURE_RTM))
 468                 srbds_mitigation = SRBDS_MITIGATION_TSX_OFF;
 469         else if (boot_cpu_has(X86_FEATURE_HYPERVISOR))
 470                 srbds_mitigation = SRBDS_MITIGATION_HYPERVISOR;
 471         else if (!boot_cpu_has(X86_FEATURE_SRBDS_CTRL))
 472                 srbds_mitigation = SRBDS_MITIGATION_UCODE_NEEDED;
 473         else if (cpu_mitigations_off() || srbds_off)
 474                 srbds_mitigation = SRBDS_MITIGATION_OFF;
 475
 476         update_srbds_msr();
 477         pr_info("%s\n", srbds_strings[srbds_mitigation]);
 478 }
 479
 480 static int __init srbds_parse_cmdline(char *str)
 481 {
 482         if (!str)
 483                 return -EINVAL;
 484
 485         if (!boot_cpu_has_bug(X86_BUG_SRBDS))
 486                 return 0;
 487
 488         srbds_off = !strcmp(str, "off");
 489         return 0;
 490 }
 491 early_param("srbds", srbds_parse_cmdline);
 492
 493 #undef pr_fmt
 494 #define pr_fmt(fmt)     "Spectre V1 : " fmt
 495
 496 enum spectre_v1_mitigation {
 497         SPECTRE_V1_MITIGATION_NONE,
 498         SPECTRE_V1_MITIGATION_AUTO,
 499 };
 500
 501 static enum spectre_v1_mitigation spectre_v1_mitigation __ro_after_init =
 502         SPECTRE_V1_MITIGATION_AUTO;
 503
 504 static const char * const spectre_v1_strings[] = {
 505         [SPECTRE_V1_MITIGATION_NONE] = "Vulnerable: __user pointer sanitization and usercopy barriers only; no swapgs barriers",
 506         [SPECTRE_V1_MITIGATION_AUTO] = "Mitigation: usercopy/swapgs barriers and __user pointer sanitization",
 507 };
 508
 509 /*
 510  * Does SMAP provide full mitigation against speculative kernel access to
 511  * userspace?
 512  */
 513 static bool smap_works_speculatively(void)
 514 {
 515         if (!boot_cpu_has(X86_FEATURE_SMAP))
 516                 return false;
 517
 518         /*
 519          * On CPUs which are vulnerable to Meltdown, SMAP does not
 520          * prevent speculative access to user data in the L1 cache.
 521          * Consider SMAP to be non-functional as a mitigation on these
 522          * CPUs.
 523          */
 524         if (boot_cpu_has(X86_BUG_CPU_MELTDOWN))
 525                 return false;
 526
 527         return true;
 528 }
 529
 530 static void __init spectre_v1_select_mitigation(void)
 531 {
 532         if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V1) || cpu_mitigations_off()) {
 533                 spectre_v1_mitigation = SPECTRE_V1_MITIGATION_NONE;
 534                 return;
 535         }
 536
 537         if (spectre_v1_mitigation == SPECTRE_V1_MITIGATION_AUTO) {
 538                 /*
 539                  * With Spectre v1, a user can speculatively control either
 540                  * path of a conditional swapgs with a user-controlled GS
 541                  * value.  The mitigation is to add lfences to both code paths.
 542                  *
 543                  * If FSGSBASE is enabled, the user can put a kernel address in
 544                  * GS, in which case SMAP provides no protection.
 545                  *
 546                  * [ NOTE: Don't check for X86_FEATURE_FSGSBASE until the
 547                  *         FSGSBASE enablement patches have been merged. ]
 548                  *
 549                  * If FSGSBASE is disabled, the user can only put a user space
 550                  * address in GS.  That makes an attack harder, but still
 551                  * possible if there's no SMAP protection.
 552                  */
 553                 if (!smap_works_speculatively()) {
 554                         /*
 555                          * Mitigation can be provided from SWAPGS itself or
 556                          * PTI as the CR3 write in the Meltdown mitigation
 557                          * is serializing.
 558                          *
 559                          * If neither is there, mitigate with an LFENCE to
 560                          * stop speculation through swapgs.
 561                          */
 562                         if (boot_cpu_has_bug(X86_BUG_SWAPGS) &&
 563                             !boot_cpu_has(X86_FEATURE_PTI))
 564                                 setup_force_cpu_cap(X86_FEATURE_FENCE_SWAPGS_USER);
 565
 566                         /*
 567                          * Enable lfences in the kernel entry (non-swapgs)
 568                          * paths, to prevent user entry from speculatively
 569                          * skipping swapgs.
 570                          */
 571                         setup_force_cpu_cap(X86_FEATURE_FENCE_SWAPGS_KERNEL);
 572                 }
 573         }
 574
 575         pr_info("%s\n", spectre_v1_strings[spectre_v1_mitigation]);
 576 }
 577
 578 static int __init nospectre_v1_cmdline(char *str)
 579 {
 580         spectre_v1_mitigation = SPECTRE_V1_MITIGATION_NONE;
 581         return 0;
 582 }
 583 early_param("nospectre_v1", nospectre_v1_cmdline);
 584
 585 #undef pr_fmt
 586 #define pr_fmt(fmt)     "Spectre V2 : " fmt
 587
 588 static enum spectre_v2_mitigation spectre_v2_enabled __ro_after_init =
 589         SPECTRE_V2_NONE;
 590
 591 static enum spectre_v2_user_mitigation spectre_v2_user_stibp __ro_after_init =
 592         SPECTRE_V2_USER_NONE;
 593 static enum spectre_v2_user_mitigation spectre_v2_user_ibpb __ro_after_init =
 594         SPECTRE_V2_USER_NONE;
 595
 596 #ifdef CONFIG_RETPOLINE
 597 static bool spectre_v2_bad_module;
 598
 599 bool retpoline_module_ok(bool has_retpoline)
 600 {
 601         if (spectre_v2_enabled == SPECTRE_V2_NONE || has_retpoline)
 602                 return true;
 603
 604         pr_err("System may be vulnerable to spectre v2\n");
 605         spectre_v2_bad_module = true;
 606         return false;
 607 }
 608
 609 static inline const char *spectre_v2_module_string(void)
 610 {
 611         return spectre_v2_bad_module ? " - vulnerable module loaded" : "";
 612 }
 613 #else
 614 static inline const char *spectre_v2_module_string(void) { return ""; }
 615 #endif
 616
 617 static inline bool match_option(const char *arg, int arglen, const char *opt)
 618 {
 619         int len = strlen(opt);
 620
 621         return len == arglen && !strncmp(arg, opt, len);
 622 }
 623
 624 /* The kernel command line selection for spectre v2 */
 625 enum spectre_v2_mitigation_cmd {
 626         SPECTRE_V2_CMD_NONE,
 627         SPECTRE_V2_CMD_AUTO,
 628         SPECTRE_V2_CMD_FORCE,
 629         SPECTRE_V2_CMD_RETPOLINE,
 630         SPECTRE_V2_CMD_RETPOLINE_GENERIC,
 631         SPECTRE_V2_CMD_RETPOLINE_AMD,
 632 };
 633
 634 enum spectre_v2_user_cmd {
 635         SPECTRE_V2_USER_CMD_NONE,
 636         SPECTRE_V2_USER_CMD_AUTO,
 637         SPECTRE_V2_USER_CMD_FORCE,
 638         SPECTRE_V2_USER_CMD_PRCTL,
 639         SPECTRE_V2_USER_CMD_PRCTL_IBPB,
 640         SPECTRE_V2_USER_CMD_SECCOMP,
 641         SPECTRE_V2_USER_CMD_SECCOMP_IBPB,
 642 };
 643
 644 static const char * const spectre_v2_user_strings[] = {
 645         [SPECTRE_V2_USER_NONE]                  = "User space: Vulnerable",
 646         [SPECTRE_V2_USER_STRICT]                = "User space: Mitigation: STIBP protection",
 647         [SPECTRE_V2_USER_STRICT_PREFERRED]      = "User space: Mitigation: STIBP always-on protection",
 648         [SPECTRE_V2_USER_PRCTL]                 = "User space: Mitigation: STIBP via prctl",
 649         [SPECTRE_V2_USER_SECCOMP]               = "User space: Mitigation: STIBP via seccomp and prctl",
 650 };
 651
 652 static const struct {
 653         const char                      *option;
 654         enum spectre_v2_user_cmd        cmd;
 655         bool                            secure;
 656 } v2_user_options[] __initconst = {
 657         { "auto",               SPECTRE_V2_USER_CMD_AUTO,               false },
 658         { "off",                SPECTRE_V2_USER_CMD_NONE,               false },
 659         { "on",                 SPECTRE_V2_USER_CMD_FORCE,              true  },
 660         { "prctl",              SPECTRE_V2_USER_CMD_PRCTL,              false },
 661         { "prctl,ibpb",         SPECTRE_V2_USER_CMD_PRCTL_IBPB,         false },
 662         { "seccomp",            SPECTRE_V2_USER_CMD_SECCOMP,            false },
 663         { "seccomp,ibpb",       SPECTRE_V2_USER_CMD_SECCOMP_IBPB,       false },
 664 };
 665
 666 static void __init spec_v2_user_print_cond(const char *reason, bool secure)
 667 {
 668         if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2) != secure)
 669                 pr_info("spectre_v2_user=%s forced on command line.\n", reason);
 670 }
 671
 672 static enum spectre_v2_user_cmd __init
 673 spectre_v2_parse_user_cmdline(enum spectre_v2_mitigation_cmd v2_cmd)
 674 {
 675         char arg[20];
 676         int ret, i;
 677
 678         switch (v2_cmd) {
 679         case SPECTRE_V2_CMD_NONE:
 680                 return SPECTRE_V2_USER_CMD_NONE;
 681         case SPECTRE_V2_CMD_FORCE:
 682                 return SPECTRE_V2_USER_CMD_FORCE;
 683         default:
 684                 break;
 685         }
 686
 687         ret = cmdline_find_option(boot_command_line, "spectre_v2_user",
 688                                   arg, sizeof(arg));
 689         if (ret < 0)
 690                 return SPECTRE_V2_USER_CMD_AUTO;
 691
 692         for (i = 0; i < ARRAY_SIZE(v2_user_options); i++) {
 693                 if (match_option(arg, ret, v2_user_options[i].option)) {
 694                         spec_v2_user_print_cond(v2_user_options[i].option,
 695                                                 v2_user_options[i].secure);
 696                         return v2_user_options[i].cmd;
 697                 }
 698         }
 699
 700         pr_err("Unknown user space protection option (%s). Switching to AUTO select\n", arg);
 701         return SPECTRE_V2_USER_CMD_AUTO;
 702 }
 703
 704 static void __init
 705 spectre_v2_user_select_mitigation(enum spectre_v2_mitigation_cmd v2_cmd)
 706 {
 707         enum spectre_v2_user_mitigation mode = SPECTRE_V2_USER_NONE;
 708         bool smt_possible = IS_ENABLED(CONFIG_SMP);
 709         enum spectre_v2_user_cmd cmd;
 710
 711         if (!boot_cpu_has(X86_FEATURE_IBPB) && !boot_cpu_has(X86_FEATURE_STIBP))
 712                 return;
 713
 714         if (cpu_smt_control == CPU_SMT_FORCE_DISABLED ||
 715             cpu_smt_control == CPU_SMT_NOT_SUPPORTED)
 716                 smt_possible = false;
 717
 718         cmd = spectre_v2_parse_user_cmdline(v2_cmd);
 719         switch (cmd) {
 720         case SPECTRE_V2_USER_CMD_NONE:
 721                 goto set_mode;
 722         case SPECTRE_V2_USER_CMD_FORCE:
 723                 mode = SPECTRE_V2_USER_STRICT;
 724                 break;
 725         case SPECTRE_V2_USER_CMD_PRCTL:
 726         case SPECTRE_V2_USER_CMD_PRCTL_IBPB:
 727                 mode = SPECTRE_V2_USER_PRCTL;
 728                 break;
 729         case SPECTRE_V2_USER_CMD_AUTO:
 730         case SPECTRE_V2_USER_CMD_SECCOMP:
 731         case SPECTRE_V2_USER_CMD_SECCOMP_IBPB:
 732                 if (IS_ENABLED(CONFIG_SECCOMP))
 733                         mode = SPECTRE_V2_USER_SECCOMP;
 734                 else
 735                         mode = SPECTRE_V2_USER_PRCTL;
 736                 break;
 737         }
 738
 739         /* Initialize Indirect Branch Prediction Barrier */
 740         if (boot_cpu_has(X86_FEATURE_IBPB)) {
 741                 setup_force_cpu_cap(X86_FEATURE_USE_IBPB);
 742
 743                 switch (cmd) {
 744                 case SPECTRE_V2_USER_CMD_FORCE:
 745                 case SPECTRE_V2_USER_CMD_PRCTL_IBPB:
 746                 case SPECTRE_V2_USER_CMD_SECCOMP_IBPB:
 747                         static_branch_enable(&switch_mm_always_ibpb);
 748                         break;
 749                 case SPECTRE_V2_USER_CMD_PRCTL:
 750                 case SPECTRE_V2_USER_CMD_AUTO:
 751                 case SPECTRE_V2_USER_CMD_SECCOMP:
 752                         static_branch_enable(&switch_mm_cond_ibpb);
 753                         break;
 754                 default:
 755                         break;
 756                 }
 757
 758                 pr_info("mitigation: Enabling %s Indirect Branch Prediction Barrier\n",
 759                         static_key_enabled(&switch_mm_always_ibpb) ?
 760                         "always-on" : "conditional");
 761
 762                 spectre_v2_user_ibpb = mode;
 763         }
 764
 765         /*
 766          * If enhanced IBRS is enabled or SMT impossible, STIBP is not
 767          * required.
 768          */
 769         if (!smt_possible || spectre_v2_enabled == SPECTRE_V2_IBRS_ENHANCED)
 770                 return;
 771
 772         /*
 773          * At this point, an STIBP mode other than "off" has been set.
 774          * If STIBP support is not being forced, check if STIBP always-on
 775          * is preferred.
 776          */
 777         if (mode != SPECTRE_V2_USER_STRICT &&
 778             boot_cpu_has(X86_FEATURE_AMD_STIBP_ALWAYS_ON))
 779                 mode = SPECTRE_V2_USER_STRICT_PREFERRED;
 780
 781         /*
 782          * If STIBP is not available, clear the STIBP mode.
 783          */
 784         if (!boot_cpu_has(X86_FEATURE_STIBP))
 785                 mode = SPECTRE_V2_USER_NONE;
 786
 787         spectre_v2_user_stibp = mode;
 788
 789 set_mode:
 790         pr_info("%s\n", spectre_v2_user_strings[mode]);
 791 }
 792
 793 static const char * const spectre_v2_strings[] = {
 794         [SPECTRE_V2_NONE]                       = "Vulnerable",
 795         [SPECTRE_V2_RETPOLINE_GENERIC]          = "Mitigation: Full generic retpoline",
 796         [SPECTRE_V2_RETPOLINE_AMD]              = "Mitigation: Full AMD retpoline",
 797         [SPECTRE_V2_IBRS_ENHANCED]              = "Mitigation: Enhanced IBRS",
 798 };
 799
 800 static const struct {
 801         const char *option;
 802         enum spectre_v2_mitigation_cmd cmd;
 803         bool secure;
 804 } mitigation_options[] __initconst = {
 805         { "off",                SPECTRE_V2_CMD_NONE,              false },
 806         { "on",                 SPECTRE_V2_CMD_FORCE,             true  },
 807         { "retpoline",          SPECTRE_V2_CMD_RETPOLINE,         false },
 808         { "retpoline,amd",      SPECTRE_V2_CMD_RETPOLINE_AMD,     false },
 809         { "retpoline,generic",  SPECTRE_V2_CMD_RETPOLINE_GENERIC, false },
 810         { "auto",               SPECTRE_V2_CMD_AUTO,              false },
 811 };
 812
 813 static void __init spec_v2_print_cond(const char *reason, bool secure)
 814 {
 815         if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2) != secure)
 816                 pr_info("%s selected on command line.\n", reason);
 817 }
 818
 819 static enum spectre_v2_mitigation_cmd __init spectre_v2_parse_cmdline(void)
 820 {
 821         enum spectre_v2_mitigation_cmd cmd = SPECTRE_V2_CMD_AUTO;
 822         char arg[20];
 823         int ret, i;
 824
 825         if (cmdline_find_option_bool(boot_command_line, "nospectre_v2") ||
 826             cpu_mitigations_off())
 827                 return SPECTRE_V2_CMD_NONE;
 828
 829         ret = cmdline_find_option(boot_command_line, "spectre_v2", arg, sizeof(arg));
 830         if (ret < 0)
 831                 return SPECTRE_V2_CMD_AUTO;
 832
 833         for (i = 0; i < ARRAY_SIZE(mitigation_options); i++) {
 834                 if (!match_option(arg, ret, mitigation_options[i].option))
 835                         continue;
 836                 cmd = mitigation_options[i].cmd;
 837                 break;
 838         }
 839
 840         if (i >= ARRAY_SIZE(mitigation_options)) {
 841                 pr_err("unknown option (%s). Switching to AUTO select\n", arg);
 842                 return SPECTRE_V2_CMD_AUTO;
 843         }
 844
 845         if ((cmd == SPECTRE_V2_CMD_RETPOLINE ||
 846              cmd == SPECTRE_V2_CMD_RETPOLINE_AMD ||
 847              cmd == SPECTRE_V2_CMD_RETPOLINE_GENERIC) &&
 848             !IS_ENABLED(CONFIG_RETPOLINE)) {
 849                 pr_err("%s selected but not compiled in. Switching to AUTO select\n", mitigation_options[i].option);
 850                 return SPECTRE_V2_CMD_AUTO;
 851         }
 852
 853         if (cmd == SPECTRE_V2_CMD_RETPOLINE_AMD &&
 854             boot_cpu_data.x86_vendor != X86_VENDOR_HYGON &&
 855             boot_cpu_data.x86_vendor != X86_VENDOR_AMD) {
 856                 pr_err("retpoline,amd selected but CPU is not AMD. Switching to AUTO select\n");
 857                 return SPECTRE_V2_CMD_AUTO;
 858         }
 859
 860         spec_v2_print_cond(mitigation_options[i].option,
 861                            mitigation_options[i].secure);
 862         return cmd;
 863 }
 864
 865 static void __init spectre_v2_select_mitigation(void)
 866 {
 867         enum spectre_v2_mitigation_cmd cmd = spectre_v2_parse_cmdline();
 868         enum spectre_v2_mitigation mode = SPECTRE_V2_NONE;
 869
 870         /*
 871          * If the CPU is not affected and the command line mode is NONE or AUTO
 872          * then nothing to do.
 873          */
 874         if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2) &&
 875             (cmd == SPECTRE_V2_CMD_NONE || cmd == SPECTRE_V2_CMD_AUTO))
 876                 return;
 877
 878         switch (cmd) {
 879         case SPECTRE_V2_CMD_NONE:
 880                 return;
 881
 882         case SPECTRE_V2_CMD_FORCE:
 883         case SPECTRE_V2_CMD_AUTO:
 884                 if (boot_cpu_has(X86_FEATURE_IBRS_ENHANCED)) {
 885                         mode = SPECTRE_V2_IBRS_ENHANCED;
 886                         /* Force it so VMEXIT will restore correctly */
 887                         x86_spec_ctrl_base |= SPEC_CTRL_IBRS;
 888                         wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
 889                         goto specv2_set_mode;
 890                 }
 891                 if (IS_ENABLED(CONFIG_RETPOLINE))
 892                         goto retpoline_auto;
 893                 break;
 894         case SPECTRE_V2_CMD_RETPOLINE_AMD:
 895                 if (IS_ENABLED(CONFIG_RETPOLINE))
 896                         goto retpoline_amd;
 897                 break;
 898         case SPECTRE_V2_CMD_RETPOLINE_GENERIC:
 899                 if (IS_ENABLED(CONFIG_RETPOLINE))
 900                         goto retpoline_generic;
 901                 break;
 902         case SPECTRE_V2_CMD_RETPOLINE:
 903                 if (IS_ENABLED(CONFIG_RETPOLINE))
 904                         goto retpoline_auto;
 905                 break;
 906         }
 907         pr_err("Spectre mitigation: kernel not compiled with retpoline; no mitigation available!");
 908         return;
 909
 910 retpoline_auto:
 911         if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD ||
 912             boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) {
 913         retpoline_amd:
 914                 if (!boot_cpu_has(X86_FEATURE_LFENCE_RDTSC)) {
 915                         pr_err("Spectre mitigation: LFENCE not serializing, switching to generic retpoline\n");
 916                         goto retpoline_generic;
 917                 }
 918                 mode = SPECTRE_V2_RETPOLINE_AMD;
 919                 setup_force_cpu_cap(X86_FEATURE_RETPOLINE_AMD);
 920                 setup_force_cpu_cap(X86_FEATURE_RETPOLINE);
 921         } else {
 922         retpoline_generic:
 923                 mode = SPECTRE_V2_RETPOLINE_GENERIC;
 924                 setup_force_cpu_cap(X86_FEATURE_RETPOLINE);
 925         }
 926
 927 specv2_set_mode:
 928         spectre_v2_enabled = mode;
 929         pr_info("%s\n", spectre_v2_strings[mode]);
 930
 931         /*
 932          * If spectre v2 protection has been enabled, unconditionally fill
 933          * RSB during a context switch; this protects against two independent
 934          * issues:
 935          *
 936          *      - RSB underflow (and switch to BTB) on Skylake+
 937          *      - SpectreRSB variant of spectre v2 on X86_BUG_SPECTRE_V2 CPUs
 938          */
 939         setup_force_cpu_cap(X86_FEATURE_RSB_CTXSW);
 940         pr_info("Spectre v2 / SpectreRSB mitigation: Filling RSB on context switch\n");
 941
 942         /*
 943          * Retpoline means the kernel is safe because it has no indirect
 944          * branches. Enhanced IBRS protects firmware too, so, enable restricted
 945          * speculation around firmware calls only when Enhanced IBRS isn't
 946          * supported.
 947          *
 948          * Use "mode" to check Enhanced IBRS instead of boot_cpu_has(), because
 949          * the user might select retpoline on the kernel command line and if
 950          * the CPU supports Enhanced IBRS, kernel might un-intentionally not
 951          * enable IBRS around firmware calls.
 952          */
 953         if (boot_cpu_has(X86_FEATURE_IBRS) && mode != SPECTRE_V2_IBRS_ENHANCED) {
 954                 setup_force_cpu_cap(X86_FEATURE_USE_IBRS_FW);
 955                 pr_info("Enabling Restricted Speculation for firmware calls\n");
 956         }
 957
 958         /* Set up IBPB and STIBP depending on the general spectre V2 command */
 959         spectre_v2_user_select_mitigation(cmd);
 960 }
 961
 962 static void update_stibp_msr(void * __unused)
 963 {
 964         wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
 965 }
 966
 967 /* Update x86_spec_ctrl_base in case SMT state changed. */
 968 static void update_stibp_strict(void)
 969 {
 970         u64 mask = x86_spec_ctrl_base & ~SPEC_CTRL_STIBP;
 971
 972         if (sched_smt_active())
 973                 mask |= SPEC_CTRL_STIBP;
 974
 975         if (mask == x86_spec_ctrl_base)
 976                 return;
 977
 978         pr_info("Update user space SMT mitigation: STIBP %s\n",
 979                 mask & SPEC_CTRL_STIBP ? "always-on" : "off");
 980         x86_spec_ctrl_base = mask;
 981         on_each_cpu(update_stibp_msr, NULL, 1);
 982 }
 983
 984 /* Update the static key controlling the evaluation of TIF_SPEC_IB */
 985 static void update_indir_branch_cond(void)
 986 {
 987         if (sched_smt_active())
 988                 static_branch_enable(&switch_to_cond_stibp);
 989         else
 990                 static_branch_disable(&switch_to_cond_stibp);
 991 }
 992
 993 #undef pr_fmt
 994 #define pr_fmt(fmt) fmt
 995
 996 /* Update the static key controlling the MDS CPU buffer clear in idle */
 997 static void update_mds_branch_idle(void)
 998 {
 999         /*
1000          * Enable the idle clearing if SMT is active on CPUs which are
1001          * affected only by MSBDS and not any other MDS variant.
1002          *
1003          * The other variants cannot be mitigated when SMT is enabled, so
1004          * clearing the buffers on idle just to prevent the Store Buffer
1005          * repartitioning leak would be a window dressing exercise.
1006          */
1007         if (!boot_cpu_has_bug(X86_BUG_MSBDS_ONLY))
1008                 return;
1009
1010         if (sched_smt_active())
1011                 static_branch_enable(&mds_idle_clear);
1012         else
1013                 static_branch_disable(&mds_idle_clear);
1014 }
1015
1016 #define MDS_MSG_SMT "MDS CPU bug present and SMT on, data leak possible. See https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/mds.html for more details.\n"
1017 #define TAA_MSG_SMT "TAA CPU bug present and SMT on, data leak possible. See https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/tsx_async_abort.html for more details.\n"
1018
1019 void cpu_bugs_smt_update(void)
1020 {
1021         mutex_lock(&spec_ctrl_mutex);
1022
1023         switch (spectre_v2_user_stibp) {
1024         case SPECTRE_V2_USER_NONE:
1025                 break;
1026         case SPECTRE_V2_USER_STRICT:
1027         case SPECTRE_V2_USER_STRICT_PREFERRED:
1028                 update_stibp_strict();
1029                 break;
1030         case SPECTRE_V2_USER_PRCTL:
1031         case SPECTRE_V2_USER_SECCOMP:
1032                 update_indir_branch_cond();
1033                 break;
1034         }
1035
1036         switch (mds_mitigation) {
1037         case MDS_MITIGATION_FULL:
1038         case MDS_MITIGATION_VMWERV:
1039                 if (sched_smt_active() && !boot_cpu_has(X86_BUG_MSBDS_ONLY))
1040                         pr_warn_once(MDS_MSG_SMT);
1041                 update_mds_branch_idle();
1042                 break;
1043         case MDS_MITIGATION_OFF:
1044                 break;
1045         }
1046
1047         switch (taa_mitigation) {
1048         case TAA_MITIGATION_VERW:
1049         case TAA_MITIGATION_UCODE_NEEDED:
1050                 if (sched_smt_active())
1051                         pr_warn_once(TAA_MSG_SMT);
1052                 break;
1053         case TAA_MITIGATION_TSX_DISABLED:
1054         case TAA_MITIGATION_OFF:
1055                 break;
1056         }
1057
1058         mutex_unlock(&spec_ctrl_mutex);
1059 }
1060
1061 #undef pr_fmt
1062 #define pr_fmt(fmt)     "Speculative Store Bypass: " fmt
1063
1064 static enum ssb_mitigation ssb_mode __ro_after_init = SPEC_STORE_BYPASS_NONE;
1065
1066 /* The kernel command line selection */
1067 enum ssb_mitigation_cmd {
1068         SPEC_STORE_BYPASS_CMD_NONE,
1069         SPEC_STORE_BYPASS_CMD_AUTO,
1070         SPEC_STORE_BYPASS_CMD_ON,
1071         SPEC_STORE_BYPASS_CMD_PRCTL,
1072         SPEC_STORE_BYPASS_CMD_SECCOMP,
1073 };
1074
1075 static const char * const ssb_strings[] = {
1076         [SPEC_STORE_BYPASS_NONE]        = "Vulnerable",
1077         [SPEC_STORE_BYPASS_DISABLE]     = "Mitigation: Speculative Store Bypass disabled",
1078         [SPEC_STORE_BYPASS_PRCTL]       = "Mitigation: Speculative Store Bypass disabled via prctl",
1079         [SPEC_STORE_BYPASS_SECCOMP]     = "Mitigation: Speculative Store Bypass disabled via prctl and seccomp",
1080 };
1081
1082 static const struct {
1083         const char *option;
1084         enum ssb_mitigation_cmd cmd;
1085 } ssb_mitigation_options[]  __initconst = {
1086         { "auto",       SPEC_STORE_BYPASS_CMD_AUTO },    /* Platform decides */
1087         { "on",         SPEC_STORE_BYPASS_CMD_ON },      /* Disable Speculative Store Bypass */
1088         { "off",        SPEC_STORE_BYPASS_CMD_NONE },    /* Don't touch Speculative Store Bypass */
1089         { "prctl",      SPEC_STORE_BYPASS_CMD_PRCTL },   /* Disable Speculative Store Bypass via prctl */
1090         { "seccomp",    SPEC_STORE_BYPASS_CMD_SECCOMP }, /* Disable Speculative Store Bypass via prctl and seccomp */
1091 };
1092
1093 static enum ssb_mitigation_cmd __init ssb_parse_cmdline(void)
1094 {
1095         enum ssb_mitigation_cmd cmd = SPEC_STORE_BYPASS_CMD_AUTO;
1096         char arg[20];
1097         int ret, i;
1098
1099         if (cmdline_find_option_bool(boot_command_line, "nospec_store_bypass_disable") ||
1100             cpu_mitigations_off()) {
1101                 return SPEC_STORE_BYPASS_CMD_NONE;
1102         } else {
1103                 ret = cmdline_find_option(boot_command_line, "spec_store_bypass_disable",
1104                                           arg, sizeof(arg));
1105                 if (ret < 0)
1106                         return SPEC_STORE_BYPASS_CMD_AUTO;
1107
1108                 for (i = 0; i < ARRAY_SIZE(ssb_mitigation_options); i++) {
1109                         if (!match_option(arg, ret, ssb_mitigation_options[i].option))
1110                                 continue;
1111
1112                         cmd = ssb_mitigation_options[i].cmd;
1113                         break;
1114                 }
1115
1116                 if (i >= ARRAY_SIZE(ssb_mitigation_options)) {
1117                         pr_err("unknown option (%s). Switching to AUTO select\n", arg);
1118                         return SPEC_STORE_BYPASS_CMD_AUTO;
1119                 }
1120         }
1121
1122         return cmd;
1123 }
1124
1125 static enum ssb_mitigation __init __ssb_select_mitigation(void)
1126 {
1127         enum ssb_mitigation mode = SPEC_STORE_BYPASS_NONE;
1128         enum ssb_mitigation_cmd cmd;
1129
1130         if (!boot_cpu_has(X86_FEATURE_SSBD))
1131                 return mode;
1132
1133         cmd = ssb_parse_cmdline();
1134         if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS) &&
1135             (cmd == SPEC_STORE_BYPASS_CMD_NONE ||
1136              cmd == SPEC_STORE_BYPASS_CMD_AUTO))
1137                 return mode;
1138
1139         switch (cmd) {
1140         case SPEC_STORE_BYPASS_CMD_AUTO:
1141         case SPEC_STORE_BYPASS_CMD_SECCOMP:
1142                 /*
1143                  * Choose prctl+seccomp as the default mode if seccomp is
1144                  * enabled.
1145                  */
1146                 if (IS_ENABLED(CONFIG_SECCOMP))
1147                         mode = SPEC_STORE_BYPASS_SECCOMP;
1148                 else
1149                         mode = SPEC_STORE_BYPASS_PRCTL;
1150                 break;
1151         case SPEC_STORE_BYPASS_CMD_ON:
1152                 mode = SPEC_STORE_BYPASS_DISABLE;
1153                 break;
1154         case SPEC_STORE_BYPASS_CMD_PRCTL:
1155                 mode = SPEC_STORE_BYPASS_PRCTL;
1156                 break;
1157         case SPEC_STORE_BYPASS_CMD_NONE:
1158                 break;
1159         }
1160
1161         /*
1162          * If SSBD is controlled by the SPEC_CTRL MSR, then set the proper
1163          * bit in the mask to allow guests to use the mitigation even in the
1164          * case where the host does not enable it.
1165          */
1166         if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) ||
1167             static_cpu_has(X86_FEATURE_AMD_SSBD)) {
1168                 x86_spec_ctrl_mask |= SPEC_CTRL_SSBD;
1169         }
1170
1171         /*
1172          * We have three CPU feature flags that are in play here:
1173          *  - X86_BUG_SPEC_STORE_BYPASS - CPU is susceptible.
1174          *  - X86_FEATURE_SSBD - CPU is able to turn off speculative store bypass
1175          *  - X86_FEATURE_SPEC_STORE_BYPASS_DISABLE - engage the mitigation
1176          */
1177         if (mode == SPEC_STORE_BYPASS_DISABLE) {
1178                 setup_force_cpu_cap(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE);
1179                 /*
1180                  * Intel uses the SPEC CTRL MSR Bit(2) for this, while AMD may
1181                  * use a completely different MSR and bit dependent on family.
1182                  */
1183                 if (!static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) &&
1184                     !static_cpu_has(X86_FEATURE_AMD_SSBD)) {
1185                         x86_amd_ssb_disable();
1186                 } else {
1187                         x86_spec_ctrl_base |= SPEC_CTRL_SSBD;
1188                         wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
1189                 }
1190         }
1191
1192         return mode;
1193 }
1194
1195 static void ssb_select_mitigation(void)
1196 {
1197         ssb_mode = __ssb_select_mitigation();
1198
1199         if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
1200                 pr_info("%s\n", ssb_strings[ssb_mode]);
1201 }
1202
1203 #undef pr_fmt
1204 #define pr_fmt(fmt)     "Speculation prctl: " fmt
1205
1206 static void task_update_spec_tif(struct task_struct *tsk)
1207 {
1208         /* Force the update of the real TIF bits */
1209         set_tsk_thread_flag(tsk, TIF_SPEC_FORCE_UPDATE);
1210
1211         /*
1212          * Immediately update the speculation control MSRs for the current
1213          * task, but for a non-current task delay setting the CPU
1214          * mitigation until it is scheduled next.
1215          *
1216          * This can only happen for SECCOMP mitigation. For PRCTL it's
1217          * always the current task.
1218          */
1219         if (tsk == current)
1220                 speculation_ctrl_update_current();
1221 }
1222
1223 static int ssb_prctl_set(struct task_struct *task, unsigned long ctrl)
1224 {
1225         if (ssb_mode != SPEC_STORE_BYPASS_PRCTL &&
1226             ssb_mode != SPEC_STORE_BYPASS_SECCOMP)
1227                 return -ENXIO;
1228
1229         switch (ctrl) {
1230         case PR_SPEC_ENABLE:
1231                 /* If speculation is force disabled, enable is not allowed */
1232                 if (task_spec_ssb_force_disable(task))
1233                         return -EPERM;
1234                 task_clear_spec_ssb_disable(task);
1235                 task_clear_spec_ssb_noexec(task);
1236                 task_update_spec_tif(task);
1237                 break;
1238         case PR_SPEC_DISABLE:
1239                 task_set_spec_ssb_disable(task);
1240                 task_clear_spec_ssb_noexec(task);
1241                 task_update_spec_tif(task);
1242                 break;
1243         case PR_SPEC_FORCE_DISABLE:
1244                 task_set_spec_ssb_disable(task);
1245                 task_set_spec_ssb_force_disable(task);
1246                 task_clear_spec_ssb_noexec(task);
1247                 task_update_spec_tif(task);
1248                 break;
1249         case PR_SPEC_DISABLE_NOEXEC:
1250                 if (task_spec_ssb_force_disable(task))
1251                         return -EPERM;
1252                 task_set_spec_ssb_disable(task);
1253                 task_set_spec_ssb_noexec(task);
1254                 task_update_spec_tif(task);
1255                 break;
1256         default:
1257                 return -ERANGE;
1258         }
1259         return 0;
1260 }
1261
1262 static int ib_prctl_set(struct task_struct *task, unsigned long ctrl)
1263 {
1264         switch (ctrl) {
1265         case PR_SPEC_ENABLE:
1266                 if (spectre_v2_user_ibpb == SPECTRE_V2_USER_NONE &&
1267                     spectre_v2_user_stibp == SPECTRE_V2_USER_NONE)
1268                         return 0;
1269                 /*
1270                  * Indirect branch speculation is always disabled in strict
1271                  * mode. It can neither be enabled if it was force-disabled
1272                  * by a  previous prctl call.
1273
1274                  */
1275                 if (spectre_v2_user_ibpb == SPECTRE_V2_USER_STRICT ||
1276                     spectre_v2_user_stibp == SPECTRE_V2_USER_STRICT ||
1277                     spectre_v2_user_stibp == SPECTRE_V2_USER_STRICT_PREFERRED ||
1278                     task_spec_ib_force_disable(task))
1279                         return -EPERM;
1280                 task_clear_spec_ib_disable(task);
1281                 task_update_spec_tif(task);
1282                 break;
1283         case PR_SPEC_DISABLE:
1284         case PR_SPEC_FORCE_DISABLE:
1285                 /*
1286                  * Indirect branch speculation is always allowed when
1287                  * mitigation is force disabled.
1288                  */
1289                 if (spectre_v2_user_ibpb == SPECTRE_V2_USER_NONE &&
1290                     spectre_v2_user_stibp == SPECTRE_V2_USER_NONE)
1291                         return -EPERM;
1292                 if (spectre_v2_user_ibpb == SPECTRE_V2_USER_STRICT ||
1293                     spectre_v2_user_stibp == SPECTRE_V2_USER_STRICT ||
1294                     spectre_v2_user_stibp == SPECTRE_V2_USER_STRICT_PREFERRED)
1295                         return 0;
1296                 task_set_spec_ib_disable(task);
1297                 if (ctrl == PR_SPEC_FORCE_DISABLE)
1298                         task_set_spec_ib_force_disable(task);
1299                 task_update_spec_tif(task);
1300                 break;
1301         default:
1302                 return -ERANGE;
1303         }
1304         return 0;
1305 }
1306
1307 int arch_prctl_spec_ctrl_set(struct task_struct *task, unsigned long which,
1308                              unsigned long ctrl)
1309 {
1310         switch (which) {
1311         case PR_SPEC_STORE_BYPASS:
1312                 return ssb_prctl_set(task, ctrl);
1313         case PR_SPEC_INDIRECT_BRANCH:
1314                 return ib_prctl_set(task, ctrl);
1315         default:
1316                 return -ENODEV;
1317         }
1318 }
1319
1320 #ifdef CONFIG_SECCOMP
1321 void arch_seccomp_spec_mitigate(struct task_struct *task)
1322 {
1323         if (ssb_mode == SPEC_STORE_BYPASS_SECCOMP)
1324                 ssb_prctl_set(task, PR_SPEC_FORCE_DISABLE);
1325         if (spectre_v2_user_ibpb == SPECTRE_V2_USER_SECCOMP ||
1326             spectre_v2_user_stibp == SPECTRE_V2_USER_SECCOMP)
1327                 ib_prctl_set(task, PR_SPEC_FORCE_DISABLE);
1328 }
1329 #endif
1330
1331 static int ssb_prctl_get(struct task_struct *task)
1332 {
1333         switch (ssb_mode) {
1334         case SPEC_STORE_BYPASS_DISABLE:
1335                 return PR_SPEC_DISABLE;
1336         case SPEC_STORE_BYPASS_SECCOMP:
1337         case SPEC_STORE_BYPASS_PRCTL:
1338                 if (task_spec_ssb_force_disable(task))
1339                         return PR_SPEC_PRCTL | PR_SPEC_FORCE_DISABLE;
1340                 if (task_spec_ssb_noexec(task))
1341                         return PR_SPEC_PRCTL | PR_SPEC_DISABLE_NOEXEC;
1342                 if (task_spec_ssb_disable(task))
1343                         return PR_SPEC_PRCTL | PR_SPEC_DISABLE;
1344                 return PR_SPEC_PRCTL | PR_SPEC_ENABLE;
1345         default:
1346                 if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
1347                         return PR_SPEC_ENABLE;
1348                 return PR_SPEC_NOT_AFFECTED;
1349         }
1350 }
1351
1352 static int ib_prctl_get(struct task_struct *task)
1353 {
1354         if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2))
1355                 return PR_SPEC_NOT_AFFECTED;
1356
1357         if (spectre_v2_user_ibpb == SPECTRE_V2_USER_NONE &&
1358             spectre_v2_user_stibp == SPECTRE_V2_USER_NONE)
1359                 return PR_SPEC_ENABLE;
1360         else if (spectre_v2_user_ibpb == SPECTRE_V2_USER_STRICT ||
1361             spectre_v2_user_stibp == SPECTRE_V2_USER_STRICT ||
1362             spectre_v2_user_stibp == SPECTRE_V2_USER_STRICT_PREFERRED)
1363                 return PR_SPEC_DISABLE;
1364         else if (spectre_v2_user_ibpb == SPECTRE_V2_USER_PRCTL ||
1365             spectre_v2_user_ibpb == SPECTRE_V2_USER_SECCOMP ||
1366             spectre_v2_user_stibp == SPECTRE_V2_USER_PRCTL ||
1367             spectre_v2_user_stibp == SPECTRE_V2_USER_SECCOMP) {
1368                 if (task_spec_ib_force_disable(task))
1369                         return PR_SPEC_PRCTL | PR_SPEC_FORCE_DISABLE;
1370                 if (task_spec_ib_disable(task))
1371                         return PR_SPEC_PRCTL | PR_SPEC_DISABLE;
1372                 return PR_SPEC_PRCTL | PR_SPEC_ENABLE;
1373         } else
1374                 return PR_SPEC_NOT_AFFECTED;
1375 }
1376
1377 int arch_prctl_spec_ctrl_get(struct task_struct *task, unsigned long which)
1378 {
1379         switch (which) {
1380         case PR_SPEC_STORE_BYPASS:
1381                 return ssb_prctl_get(task);
1382         case PR_SPEC_INDIRECT_BRANCH:
1383                 return ib_prctl_get(task);
1384         default:
1385                 return -ENODEV;
1386         }
1387 }
1388
1389 void x86_spec_ctrl_setup_ap(void)
1390 {
1391         if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL))
1392                 wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
1393
1394         if (ssb_mode == SPEC_STORE_BYPASS_DISABLE)
1395                 x86_amd_ssb_disable();
1396 }
1397
1398 bool itlb_multihit_kvm_mitigation;
1399 EXPORT_SYMBOL_GPL(itlb_multihit_kvm_mitigation);
1400
1401 #undef pr_fmt
1402 #define pr_fmt(fmt)     "L1TF: " fmt
1403
1404 /* Default mitigation for L1TF-affected CPUs */
1405 enum l1tf_mitigations l1tf_mitigation __ro_after_init = L1TF_MITIGATION_FLUSH;
1406 #if IS_ENABLED(CONFIG_KVM_INTEL)
1407 EXPORT_SYMBOL_GPL(l1tf_mitigation);
1408 #endif
1409 enum vmx_l1d_flush_state l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_AUTO;
1410 EXPORT_SYMBOL_GPL(l1tf_vmx_mitigation);
1411
1412 /*
1413  * These CPUs all support 44bits physical address space internally in the
1414  * cache but CPUID can report a smaller number of physical address bits.
1415  *
1416  * The L1TF mitigation uses the top most address bit for the inversion of
1417  * non present PTEs. When the installed memory reaches into the top most
1418  * address bit due to memory holes, which has been observed on machines
1419  * which report 36bits physical address bits and have 32G RAM installed,
1420  * then the mitigation range check in l1tf_select_mitigation() triggers.
1421  * This is a false positive because the mitigation is still possible due to
1422  * the fact that the cache uses 44bit internally. Use the cache bits
1423  * instead of the reported physical bits and adjust them on the affected
1424  * machines to 44bit if the reported bits are less than 44.
1425  */
1426 static void override_cache_bits(struct cpuinfo_x86 *c)
1427 {
1428         if (c->x86 != 6)
1429                 return;
1430
1431         switch (c->x86_model) {
1432         case INTEL_FAM6_NEHALEM:
1433         case INTEL_FAM6_WESTMERE:
1434         case INTEL_FAM6_SANDYBRIDGE:
1435         case INTEL_FAM6_IVYBRIDGE:
1436         case INTEL_FAM6_HASWELL:
1437         case INTEL_FAM6_HASWELL_L:
1438         case INTEL_FAM6_HASWELL_G:
1439         case INTEL_FAM6_BROADWELL:
1440         case INTEL_FAM6_BROADWELL_G:
1441         case INTEL_FAM6_SKYLAKE_L:
1442         case INTEL_FAM6_SKYLAKE:
1443         case INTEL_FAM6_KABYLAKE_L:
1444         case INTEL_FAM6_KABYLAKE:
1445                 if (c->x86_cache_bits < 44)
1446                         c->x86_cache_bits = 44;
1447                 break;
1448         }
1449 }
1450
1451 static void __init l1tf_select_mitigation(void)
1452 {
1453         u64 half_pa;
1454
1455         if (!boot_cpu_has_bug(X86_BUG_L1TF))
1456                 return;
1457
1458         if (cpu_mitigations_off())
1459                 l1tf_mitigation = L1TF_MITIGATION_OFF;
1460         else if (cpu_mitigations_auto_nosmt())
1461                 l1tf_mitigation = L1TF_MITIGATION_FLUSH_NOSMT;
1462
1463         override_cache_bits(&boot_cpu_data);
1464
1465         switch (l1tf_mitigation) {
1466         case L1TF_MITIGATION_OFF:
1467         case L1TF_MITIGATION_FLUSH_NOWARN:
1468         case L1TF_MITIGATION_FLUSH:
1469                 break;
1470         case L1TF_MITIGATION_FLUSH_NOSMT:
1471         case L1TF_MITIGATION_FULL:
1472                 cpu_smt_disable(false);
1473                 break;
1474         case L1TF_MITIGATION_FULL_FORCE:
1475                 cpu_smt_disable(true);
1476                 break;
1477         }
1478
1479 #if CONFIG_PGTABLE_LEVELS == 2
1480         pr_warn("Kernel not compiled for PAE. No mitigation for L1TF\n");
1481         return;
1482 #endif
1483
1484         half_pa = (u64)l1tf_pfn_limit() << PAGE_SHIFT;
1485         if (l1tf_mitigation != L1TF_MITIGATION_OFF &&
1486                         e820__mapped_any(half_pa, ULLONG_MAX - half_pa, E820_TYPE_RAM)) {
1487                 pr_warn("System has more than MAX_PA/2 memory. L1TF mitigation not effective.\n");
1488                 pr_info("You may make it effective by booting the kernel with mem=%llu parameter.\n",
1489                                 half_pa);
1490                 pr_info("However, doing so will make a part of your RAM unusable.\n");
1491                 pr_info("Reading https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html might help you decide.\n");
1492                 return;
1493         }
1494
1495         setup_force_cpu_cap(X86_FEATURE_L1TF_PTEINV);
1496 }
1497
1498 static int __init l1tf_cmdline(char *str)
1499 {
1500         if (!boot_cpu_has_bug(X86_BUG_L1TF))
1501                 return 0;
1502
1503         if (!str)
1504                 return -EINVAL;
1505
1506         if (!strcmp(str, "off"))
1507                 l1tf_mitigation = L1TF_MITIGATION_OFF;
1508         else if (!strcmp(str, "flush,nowarn"))
1509                 l1tf_mitigation = L1TF_MITIGATION_FLUSH_NOWARN;
1510         else if (!strcmp(str, "flush"))
1511                 l1tf_mitigation = L1TF_MITIGATION_FLUSH;
1512         else if (!strcmp(str, "flush,nosmt"))
1513                 l1tf_mitigation = L1TF_MITIGATION_FLUSH_NOSMT;
1514         else if (!strcmp(str, "full"))
1515                 l1tf_mitigation = L1TF_MITIGATION_FULL;
1516         else if (!strcmp(str, "full,force"))
1517                 l1tf_mitigation = L1TF_MITIGATION_FULL_FORCE;
1518
1519         return 0;
1520 }
1521 early_param("l1tf", l1tf_cmdline);
1522
1523 #undef pr_fmt
1524 #define pr_fmt(fmt) fmt
1525
1526 #ifdef CONFIG_SYSFS
1527
1528 #define L1TF_DEFAULT_MSG "Mitigation: PTE Inversion"
1529
1530 #if IS_ENABLED(CONFIG_KVM_INTEL)
1531 static const char * const l1tf_vmx_states[] = {
1532         [VMENTER_L1D_FLUSH_AUTO]                = "auto",
1533         [VMENTER_L1D_FLUSH_NEVER]               = "vulnerable",
1534         [VMENTER_L1D_FLUSH_COND]                = "conditional cache flushes",
1535         [VMENTER_L1D_FLUSH_ALWAYS]              = "cache flushes",
1536         [VMENTER_L1D_FLUSH_EPT_DISABLED]        = "EPT disabled",
1537         [VMENTER_L1D_FLUSH_NOT_REQUIRED]        = "flush not necessary"
1538 };
1539
1540 static ssize_t l1tf_show_state(char *buf)
1541 {
1542         if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_AUTO)
1543                 return sprintf(buf, "%s\n", L1TF_DEFAULT_MSG);
1544
1545         if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_EPT_DISABLED ||
1546             (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_NEVER &&
1547              sched_smt_active())) {
1548                 return sprintf(buf, "%s; VMX: %s\n", L1TF_DEFAULT_MSG,
1549                                l1tf_vmx_states[l1tf_vmx_mitigation]);
1550         }
1551
1552         return sprintf(buf, "%s; VMX: %s, SMT %s\n", L1TF_DEFAULT_MSG,
1553                        l1tf_vmx_states[l1tf_vmx_mitigation],
1554                        sched_smt_active() ? "vulnerable" : "disabled");
1555 }
1556
1557 static ssize_t itlb_multihit_show_state(char *buf)
1558 {
1559         if (itlb_multihit_kvm_mitigation)
1560                 return sprintf(buf, "KVM: Mitigation: Split huge pages\n");
1561         else
1562                 return sprintf(buf, "KVM: Vulnerable\n");
1563 }
1564 #else
1565 static ssize_t l1tf_show_state(char *buf)
1566 {
1567         return sprintf(buf, "%s\n", L1TF_DEFAULT_MSG);
1568 }
1569
1570 static ssize_t itlb_multihit_show_state(char *buf)
1571 {
1572         return sprintf(buf, "Processor vulnerable\n");
1573 }
1574 #endif
1575
1576 static ssize_t mds_show_state(char *buf)
1577 {
1578         if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) {
1579                 return sprintf(buf, "%s; SMT Host state unknown\n",
1580                                mds_strings[mds_mitigation]);
1581         }
1582
1583         if (boot_cpu_has(X86_BUG_MSBDS_ONLY)) {
1584                 return sprintf(buf, "%s; SMT %s\n", mds_strings[mds_mitigation],
1585                                (mds_mitigation == MDS_MITIGATION_OFF ? "vulnerable" :
1586                                 sched_smt_active() ? "mitigated" : "disabled"));
1587         }
1588
1589         return sprintf(buf, "%s; SMT %s\n", mds_strings[mds_mitigation],
1590                        sched_smt_active() ? "vulnerable" : "disabled");
1591 }
1592
1593 static ssize_t tsx_async_abort_show_state(char *buf)
1594 {
1595         if ((taa_mitigation == TAA_MITIGATION_TSX_DISABLED) ||
1596             (taa_mitigation == TAA_MITIGATION_OFF))
1597                 return sprintf(buf, "%s\n", taa_strings[taa_mitigation]);
1598
1599         if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) {
1600                 return sprintf(buf, "%s; SMT Host state unknown\n",
1601                                taa_strings[taa_mitigation]);
1602         }
1603
1604         return sprintf(buf, "%s; SMT %s\n", taa_strings[taa_mitigation],
1605                        sched_smt_active() ? "vulnerable" : "disabled");
1606 }
1607
1608 static char *stibp_state(void)
1609 {
1610         if (spectre_v2_enabled == SPECTRE_V2_IBRS_ENHANCED)
1611                 return "";
1612
1613         switch (spectre_v2_user_stibp) {
1614         case SPECTRE_V2_USER_NONE:
1615                 return ", STIBP: disabled";
1616         case SPECTRE_V2_USER_STRICT:
1617                 return ", STIBP: forced";
1618         case SPECTRE_V2_USER_STRICT_PREFERRED:
1619                 return ", STIBP: always-on";
1620         case SPECTRE_V2_USER_PRCTL:
1621         case SPECTRE_V2_USER_SECCOMP:
1622                 if (static_key_enabled(&switch_to_cond_stibp))
1623                         return ", STIBP: conditional";
1624         }
1625         return "";
1626 }
1627
1628 static char *ibpb_state(void)
1629 {
1630         if (boot_cpu_has(X86_FEATURE_IBPB)) {
1631                 if (static_key_enabled(&switch_mm_always_ibpb))
1632                         return ", IBPB: always-on";
1633                 if (static_key_enabled(&switch_mm_cond_ibpb))
1634                         return ", IBPB: conditional";
1635                 return ", IBPB: disabled";
1636         }
1637         return "";
1638 }
1639
1640 static ssize_t srbds_show_state(char *buf)
1641 {
1642         return sprintf(buf, "%s\n", srbds_strings[srbds_mitigation]);
1643 }
1644
1645 static ssize_t cpu_show_common(struct device *dev, struct device_attribute *attr,
1646                                char *buf, unsigned int bug)
1647 {
1648         if (!boot_cpu_has_bug(bug))
1649                 return sprintf(buf, "Not affected\n");
1650
1651         switch (bug) {
1652         case X86_BUG_CPU_MELTDOWN:
1653                 if (boot_cpu_has(X86_FEATURE_PTI))
1654                         return sprintf(buf, "Mitigation: PTI\n");
1655
1656                 if (hypervisor_is_type(X86_HYPER_XEN_PV))
1657                         return sprintf(buf, "Unknown (XEN PV detected, hypervisor mitigation required)\n");
1658
1659                 break;
1660
1661         case X86_BUG_SPECTRE_V1:
1662                 return sprintf(buf, "%s\n", spectre_v1_strings[spectre_v1_mitigation]);
1663
1664         case X86_BUG_SPECTRE_V2:
1665                 return sprintf(buf, "%s%s%s%s%s%s\n", spectre_v2_strings[spectre_v2_enabled],
1666                                ibpb_state(),
1667                                boot_cpu_has(X86_FEATURE_USE_IBRS_FW) ? ", IBRS_FW" : "",
1668                                stibp_state(),
1669                                boot_cpu_has(X86_FEATURE_RSB_CTXSW) ? ", RSB filling" : "",
1670                                spectre_v2_module_string());
1671
1672         case X86_BUG_SPEC_STORE_BYPASS:
1673                 return sprintf(buf, "%s\n", ssb_strings[ssb_mode]);
1674
1675         case X86_BUG_L1TF:
1676                 if (boot_cpu_has(X86_FEATURE_L1TF_PTEINV))
1677                         return l1tf_show_state(buf);
1678                 break;
1679
1680         case X86_BUG_MDS:
1681                 return mds_show_state(buf);
1682
1683         case X86_BUG_TAA:
1684                 return tsx_async_abort_show_state(buf);
1685
1686         case X86_BUG_ITLB_MULTIHIT:
1687                 return itlb_multihit_show_state(buf);
1688
1689         case X86_BUG_SRBDS:
1690                 return srbds_show_state(buf);
1691
1692         default:
1693                 break;
1694         }
1695
1696         return sprintf(buf, "Vulnerable\n");
1697 }
1698
1699 ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr, char *buf)
1700 {
1701         return cpu_show_common(dev, attr, buf, X86_BUG_CPU_MELTDOWN);
1702 }
1703
1704 ssize_t cpu_show_spectre_v1(struct device *dev, struct device_attribute *attr, char *buf)
1705 {
1706         return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V1);
1707 }
1708
1709 ssize_t cpu_show_spectre_v2(struct device *dev, struct device_attribute *attr, char *buf)
1710 {
1711         return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V2);
1712 }
1713
1714 ssize_t cpu_show_spec_store_bypass(struct device *dev, struct device_attribute *attr, char *buf)
1715 {
1716         return cpu_show_common(dev, attr, buf, X86_BUG_SPEC_STORE_BYPASS);
1717 }
1718
1719 ssize_t cpu_show_l1tf(struct device *dev, struct device_attribute *attr, char *buf)
1720 {
1721         return cpu_show_common(dev, attr, buf, X86_BUG_L1TF);
1722 }
1723
1724 ssize_t cpu_show_mds(struct device *dev, struct device_attribute *attr, char *buf)
1725 {
1726         return cpu_show_common(dev, attr, buf, X86_BUG_MDS);
1727 }
1728
1729 ssize_t cpu_show_tsx_async_abort(struct device *dev, struct device_attribute *attr, char *buf)
1730 {
1731         return cpu_show_common(dev, attr, buf, X86_BUG_TAA);
1732 }
1733
1734 ssize_t cpu_show_itlb_multihit(struct device *dev, struct device_attribute *attr, char *buf)
1735 {
1736         return cpu_show_common(dev, attr, buf, X86_BUG_ITLB_MULTIHIT);
1737 }
1738
1739 ssize_t cpu_show_srbds(struct device *dev, struct device_attribute *attr, char *buf)
1740 {
1741         return cpu_show_common(dev, attr, buf, X86_BUG_SRBDS);
1742 }
1743 #endif