2 * From Coreboot file of same name
4 * Copyright (C) 2007-2009 coresystems GmbH
5 * 2012 secunet Security Networks AG
7 * SPDX-License-Identifier: GPL-2.0
10 #ifndef _ASM_SPEEDSTEP_H
11 #define _ASM_SPEEDSTEP_H
13 /* Magic value used to locate speedstep configuration in the device tree */
14 #define SPEEDSTEP_APIC_MAGIC 0xACAC
16 /* MWAIT coordination I/O base address. This must match
17 * the \_PR_.CPU0 PM base address.
19 #define PMB0_BASE 0x510
21 /* PMB1: I/O port that triggers SMI once cores are in the same state.
22 * See CSM Trigger, at PMG_CST_CONFIG_CONTROL[6:4]
24 #define PMB1_BASE 0x800
27 uint8_t dynfsb:1; /* whether this is SLFM */
28 uint8_t nonint:1; /* add .5 to ratio */
35 #define SPEEDSTEP_RATIO_SHIFT 8
36 #define SPEEDSTEP_RATIO_DYNFSB_SHIFT (7 + SPEEDSTEP_RATIO_SHIFT)
37 #define SPEEDSTEP_RATIO_DYNFSB (1 << SPEEDSTEP_RATIO_DYNFSB_SHIFT)
38 #define SPEEDSTEP_RATIO_NONINT_SHIFT (6 + SPEEDSTEP_RATIO_SHIFT)
39 #define SPEEDSTEP_RATIO_NONINT (1 << SPEEDSTEP_RATIO_NONINT_SHIFT)
40 #define SPEEDSTEP_RATIO_VALUE_MASK (0x1f << SPEEDSTEP_RATIO_SHIFT)
41 #define SPEEDSTEP_VID_MASK 0x3f
42 #define SPEEDSTEP_STATE_FROM_MSR(val, mask) ((struct sst_state){ \
43 0, /* dynfsb won't be read. */ \
44 ((val & mask) & SPEEDSTEP_RATIO_NONINT) ? 1 : 0, \
45 (((val & mask) & SPEEDSTEP_RATIO_VALUE_MASK) \
46 >> SPEEDSTEP_RATIO_SHIFT), \
47 (val & mask) & SPEEDSTEP_VID_MASK, \
48 0, /* not turbo by default */ \
49 0, /* not slfm by default */ \
50 0 /* power is hardcoded in software. */ \
52 #define SPEEDSTEP_ENCODE_STATE(state) ( \
53 ((uint16_t)(state).dynfsb << SPEEDSTEP_RATIO_DYNFSB_SHIFT) | \
54 ((uint16_t)(state).nonint << SPEEDSTEP_RATIO_NONINT_SHIFT) | \
55 ((uint16_t)(state).ratio << SPEEDSTEP_RATIO_SHIFT) | \
56 ((uint16_t)(state).vid & SPEEDSTEP_VID_MASK))
57 #define SPEEDSTEP_DOUBLE_RATIO(state) ( \
58 ((uint8_t)(state).ratio * 2) + (state).nonint)
61 struct sst_state slfm;
64 struct sst_state turbo;
67 /* Looking at core2's spec, the highest normal bus ratio for an eist enabled
68 processor is 14, the lowest is always 6. This makes 5 states with the
69 minimal step width of 2. With turbo mode and super LFM we have at most 7. */
70 #define SPEEDSTEP_MAX_NORMAL_STATES 5
71 #define SPEEDSTEP_MAX_STATES (SPEEDSTEP_MAX_NORMAL_STATES + 2)
73 /* Table of p-states for EMTTM and ACPI by decreasing performance. */
74 struct sst_state states[SPEEDSTEP_MAX_STATES];
78 void speedstep_gen_pstates(struct sst_table *);
80 #define SPEEDSTEP_MAX_POWER_YONAH 31000
81 #define SPEEDSTEP_MIN_POWER_YONAH 13100
82 #define SPEEDSTEP_MAX_POWER_MEROM 35000
83 #define SPEEDSTEP_MIN_POWER_MEROM 25000
84 #define SPEEDSTEP_SLFM_POWER_MEROM 12000
85 #define SPEEDSTEP_MAX_POWER_PENRYN 35000
86 #define SPEEDSTEP_MIN_POWER_PENRYN 15000
87 #define SPEEDSTEP_SLFM_POWER_PENRYN 12000