2 * Copyright (c) 2014 Google, Inc
4 * From Coreboot file of the same name
6 * SPDX-License-Identifier: GPL-2.0+
12 /* MTRR region types */
13 #define MTRR_TYPE_UNCACHEABLE 0
14 #define MTRR_TYPE_WRCOMB 1
15 #define MTRR_TYPE_WRTHROUGH 4
16 #define MTRR_TYPE_WRPROT 5
17 #define MTRR_TYPE_WRBACK 6
19 #define MTRR_TYPE_COUNT 7
21 #define MTRR_CAP_MSR 0x0fe
22 #define MTRR_DEF_TYPE_MSR 0x2ff
24 #define MTRR_DEF_TYPE_EN (1 << 11)
25 #define MTRR_DEF_TYPE_FIX_EN (1 << 10)
27 #define MTRR_PHYS_BASE_MSR(reg) (0x200 + 2 * (reg))
28 #define MTRR_PHYS_MASK_MSR(reg) (0x200 + 2 * (reg) + 1)
30 #define MTRR_PHYS_MASK_VALID (1 << 11)
32 #define MTRR_BASE_TYPE_MASK 0x7
34 /* Number of MTRRs supported */
37 #if !defined(__ASSEMBLER__)
40 * Information about the previous MTRR state, set up by mtrr_open()
42 * @deftype: Previous value of MTRR_DEF_TYPE_MSR
43 * @enable_cache: true if cache was enabled
51 * mtrr_open() - Prepare to adjust MTRRs
53 * Use mtrr_open() passing in a structure - this function will init it. Then
54 * when done, pass the same structure to mtrr_close() to re-enable MTRRs and
57 * @state: Empty structure to pass in to hold settings
59 void mtrr_open(struct mtrr_state *state);
62 * mtrr_open() - Clean up after adjusting MTRRs, and enable them
64 * This uses the structure containing information returned from mtrr_open().
66 * @state: Structure from mtrr_open()
68 void mtrr_close(struct mtrr_state *state);
71 * mtrr_add_request() - Add a new MTRR request
73 * This adds a request for a memory region to be set up in a particular way.
75 * @type: Requested type (MTRR_TYPE_)
76 * @start: Start address
79 * @return: 0 on success, non-zero on failure
81 int mtrr_add_request(int type, uint64_t start, uint64_t size);
84 * mtrr_commit() - set up the MTRR registers based on current requests
86 * This sets up MTRRs for the available DRAM and the requests received so far.
87 * It must be called with caches disabled.
89 * @do_caches: true if caches are currently on
91 * @return: 0 on success, non-zero on failure
93 int mtrr_commit(bool do_caches);
97 #if ((CONFIG_XIP_ROM_SIZE & (CONFIG_XIP_ROM_SIZE - 1)) != 0)
98 # error "CONFIG_XIP_ROM_SIZE is not a power of 2"
101 #if ((CONFIG_CACHE_ROM_SIZE & (CONFIG_CACHE_ROM_SIZE - 1)) != 0)
102 # error "CONFIG_CACHE_ROM_SIZE is not a power of 2"
105 #define CACHE_ROM_BASE (((1 << 20) - (CONFIG_CACHE_ROM_SIZE >> 12)) << 12)