1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Taken from the linux kernel file of the same name
6 * Graeme Russ, <graeme.russ@gmail.com>
9 #ifndef _ASM_X86_MSR_INDEX_H
10 #define _ASM_X86_MSR_INDEX_H
12 /* CPU model specific register (MSR) numbers */
14 /* x86-64 specific MSRs */
15 #define MSR_EFER 0xc0000080 /* extended feature register */
16 #define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target */
17 #define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target */
18 #define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target */
19 #define MSR_SYSCALL_MASK 0xc0000084 /* EFLAGS mask for syscall */
20 #define MSR_FS_BASE 0xc0000100 /* 64bit FS base */
21 #define MSR_GS_BASE 0xc0000101 /* 64bit GS base */
22 #define MSR_KERNEL_GS_BASE 0xc0000102 /* SwapGS GS shadow */
23 #define MSR_TSC_AUX 0xc0000103 /* Auxiliary TSC */
26 #define _EFER_SCE 0 /* SYSCALL/SYSRET */
27 #define _EFER_LME 8 /* Long mode enable */
28 #define _EFER_LMA 10 /* Long mode active (read-only) */
29 #define _EFER_NX 11 /* No execute enable */
30 #define _EFER_SVME 12 /* Enable virtualization */
31 #define _EFER_LMSLE 13 /* Long Mode Segment Limit Enable */
32 #define _EFER_FFXSR 14 /* Enable Fast FXSAVE/FXRSTOR */
34 #define EFER_SCE (1<<_EFER_SCE)
35 #define EFER_LME (1<<_EFER_LME)
36 #define EFER_LMA (1<<_EFER_LMA)
37 #define EFER_NX (1<<_EFER_NX)
38 #define EFER_SVME (1<<_EFER_SVME)
39 #define EFER_LMSLE (1<<_EFER_LMSLE)
40 #define EFER_FFXSR (1<<_EFER_FFXSR)
42 /* Intel MSRs. Some also available on other CPUs */
43 #define MSR_PIC_MSG_CONTROL 0x2e
44 #define PLATFORM_INFO_SET_TDP (1 << 29)
46 #define MSR_MTRR_CAP_MSR 0x0fe
47 #define MSR_MTRR_CAP_SMRR (1 << 11)
48 #define MSR_MTRR_CAP_WC (1 << 10)
49 #define MSR_MTRR_CAP_FIX (1 << 8)
50 #define MSR_MTRR_CAP_VCNT 0xff
52 #define MSR_IA32_PERFCTR0 0x000000c1
53 #define MSR_IA32_PERFCTR1 0x000000c2
54 #define MSR_FSB_FREQ 0x000000cd
55 #define MSR_NHM_PLATFORM_INFO 0x000000ce
57 #define MSR_NHM_SNB_PKG_CST_CFG_CTL 0x000000e2
58 #define NHM_C3_AUTO_DEMOTE (1UL << 25)
59 #define NHM_C1_AUTO_DEMOTE (1UL << 26)
60 #define ATM_LNC_C6_AUTO_DEMOTE (1UL << 25)
61 #define SNB_C1_AUTO_UNDEMOTE (1UL << 27)
62 #define SNB_C3_AUTO_UNDEMOTE (1UL << 28)
64 #define MSR_BSEL_CR_OVERCLOCK_CONTROL 0x000000cd
65 #define MSR_PLATFORM_INFO 0x000000ce
66 #define MSR_PMG_CST_CONFIG_CONTROL 0x000000e2
67 #define SINGLE_PCTL (1 << 11)
69 #define MSR_MTRRcap 0x000000fe
70 #define MSR_IA32_BBL_CR_CTL 0x00000119
71 #define MSR_IA32_BBL_CR_CTL3 0x0000011e
72 #define MSR_POWER_MISC 0x00000120
73 #define FLUSH_DL1_L2 (1 << 8)
74 #define ENABLE_ULFM_AUTOCM_MASK (1 << 2)
75 #define ENABLE_INDP_AUTOCM_MASK (1 << 3)
77 #define MSR_EMULATE_PM_TIMER 0x121
78 #define EMULATE_DELAY_OFFSET_VALUE 20
79 #define EMULATE_PM_TMR_EN (1 << 16)
80 #define EMULATE_DELAY_VALUE 0x13
82 #define MSR_IA32_SYSENTER_CS 0x00000174
83 #define MSR_IA32_SYSENTER_ESP 0x00000175
84 #define MSR_IA32_SYSENTER_EIP 0x00000176
86 #define MSR_IA32_MCG_CAP 0x00000179
87 #define MSR_IA32_MCG_STATUS 0x0000017a
88 #define MSR_IA32_MCG_CTL 0x0000017b
90 #define MSR_FLEX_RATIO 0x194
91 #define FLEX_RATIO_LOCK (1 << 20)
92 #define FLEX_RATIO_EN (1 << 16)
93 /* This is burst mode BIT 38 in IA32_MISC_ENABLE MSR at offset 1A0h */
94 #define BURST_MODE_DISABLE (1 << 6)
96 #define MSR_IA32_MISC_ENABLE 0x000001a0
98 /* MISC_ENABLE bits: architectural */
99 #define MISC_ENABLE_FAST_STRING BIT_ULL(0)
100 #define MISC_ENABLE_TCC BIT_ULL(1)
101 #define MISC_DISABLE_TURBO BIT_ULL(6)
102 #define MISC_ENABLE_EMON BIT_ULL(7)
103 #define MISC_ENABLE_BTS_UNAVAIL BIT_ULL(11)
104 #define MISC_ENABLE_PEBS_UNAVAIL BIT_ULL(12)
105 #define MISC_ENABLE_ENHANCED_SPEEDSTEP BIT_ULL(16)
106 #define MISC_ENABLE_MWAIT BIT_ULL(18)
107 #define MISC_ENABLE_LIMIT_CPUID BIT_ULL(22)
108 #define MISC_ENABLE_XTPR_DISABLE BIT_ULL(23)
109 #define MISC_ENABLE_XD_DISABLE BIT_ULL(34)
111 /* MISC_ENABLE bits: model-specific, meaning may vary from core to core */
112 #define MISC_ENABLE_X87_COMPAT BIT_ULL(2)
113 #define MISC_ENABLE_TM1 BIT_ULL(3)
114 #define MISC_ENABLE_SPLIT_LOCK_DISABLE BIT_ULL(4)
115 #define MISC_ENABLE_L3CACHE_DISABLE BIT_ULL(6)
116 #define MISC_ENABLE_SUPPRESS_LOCK BIT_ULL(8)
117 #define MISC_ENABLE_PREFETCH_DISABLE BIT_ULL(9)
118 #define MISC_ENABLE_FERR BIT_ULL(10)
119 #define MISC_ENABLE_FERR_MULTIPLEX BIT_ULL(10)
120 #define MISC_ENABLE_TM2 BIT_ULL(13)
121 #define MISC_ENABLE_ADJ_PREF_DISABLE BIT_ULL(19)
122 #define MISC_ENABLE_SPEEDSTEP_LOCK BIT_ULL(20)
123 #define MISC_ENABLE_L1D_CONTEXT BIT_ULL(24)
124 #define MISC_ENABLE_DCU_PREF_DISABLE BIT_ULL(37)
125 #define MISC_ENABLE_TURBO_DISABLE BIT_ULL(38)
126 #define MISC_ENABLE_IP_PREF_DISABLE BIT_ULL(39)
128 #define MSR_TEMPERATURE_TARGET 0x1a2
129 #define MSR_PREFETCH_CTL 0x1a4
130 #define PREFETCH_L1_DISABLE (1 << 0)
131 #define PREFETCH_L2_DISABLE (1 << 2)
132 #define MSR_OFFCORE_RSP_0 0x000001a6
133 #define MSR_OFFCORE_RSP_1 0x000001a7
134 #define MSR_MISC_PWR_MGMT 0x1aa
135 #define MISC_PWR_MGMT_EIST_HW_DIS (1 << 0)
136 #define MSR_TURBO_RATIO_LIMIT 0x000001ad
138 #define MSR_IA32_ENERGY_PERFORMANCE_BIAS 0x1b0
139 #define ENERGY_POLICY_PERFORMANCE 0
140 #define ENERGY_POLICY_NORMAL 6
141 #define ENERGY_POLICY_POWERSAVE 15
143 #define MSR_IA32_PACKAGE_THERM_STATUS 0x000001b1
145 #define PACKAGE_THERM_STATUS_PROCHOT BIT(0)
146 #define PACKAGE_THERM_STATUS_POWER_LIMIT BIT(10)
148 #define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001b2
150 #define PACKAGE_THERM_INT_HIGH_ENABLE BIT(0)
151 #define PACKAGE_THERM_INT_LOW_ENABLE BIT(1)
152 #define PACKAGE_THERM_INT_PLN_ENABLE BIT(24)
154 #define MSR_LBR_SELECT 0x000001c8
155 #define MSR_LBR_TOS 0x000001c9
156 #define MSR_IA32_PLATFORM_DCA_CAP 0x1f8
157 #define MSR_POWER_CTL 0x000001fc
158 #define MSR_LBR_NHM_FROM 0x00000680
159 #define MSR_LBR_NHM_TO 0x000006c0
160 #define MSR_LBR_CORE_FROM 0x00000040
161 #define MSR_LBR_CORE_TO 0x00000060
163 #define MSR_IA32_PEBS_ENABLE 0x000003f1
164 #define MSR_IA32_DS_AREA 0x00000600
165 #define MSR_IA32_PERF_CAPABILITIES 0x00000345
166 #define MSR_PEBS_LD_LAT_THRESHOLD 0x000003f6
168 #define MSR_MTRRfix64K_00000 0x00000250
169 #define MSR_MTRRfix16K_80000 0x00000258
170 #define MSR_MTRRfix16K_A0000 0x00000259
171 #define MSR_MTRRfix4K_C0000 0x00000268
172 #define MSR_MTRRfix4K_C8000 0x00000269
173 #define MSR_MTRRfix4K_D0000 0x0000026a
174 #define MSR_MTRRfix4K_D8000 0x0000026b
175 #define MSR_MTRRfix4K_E0000 0x0000026c
176 #define MSR_MTRRfix4K_E8000 0x0000026d
177 #define MSR_MTRRfix4K_F0000 0x0000026e
178 #define MSR_MTRRfix4K_F8000 0x0000026f
179 #define MSR_MTRRdefType 0x000002ff
181 #define MSR_IA32_CR_PAT 0x00000277
183 #define MSR_IA32_DEBUGCTLMSR 0x000001d9
184 #define MSR_IA32_LASTBRANCHFROMIP 0x000001db
185 #define MSR_IA32_LASTBRANCHTOIP 0x000001dc
186 #define MSR_IA32_LASTINTFROMIP 0x000001dd
187 #define MSR_IA32_LASTINTTOIP 0x000001de
189 /* DEBUGCTLMSR bits (others vary by model): */
190 #define DEBUGCTLMSR_LBR (1UL << 0) /* last branch recording */
191 /* single-step on branches */
192 #define DEBUGCTLMSR_BTF (1UL << 1)
193 #define DEBUGCTLMSR_TR (1UL << 6)
194 #define DEBUGCTLMSR_BTS (1UL << 7)
195 #define DEBUGCTLMSR_BTINT (1UL << 8)
196 #define DEBUGCTLMSR_BTS_OFF_OS (1UL << 9)
197 #define DEBUGCTLMSR_BTS_OFF_USR (1UL << 10)
198 #define DEBUGCTLMSR_FREEZE_LBRS_ON_PMI (1UL << 11)
200 #define MSR_IA32_POWER_CTL 0x000001fc
202 #define MSR_IA32_MC0_CTL 0x00000400
203 #define MSR_IA32_MC0_STATUS 0x00000401
204 #define MSR_IA32_MC0_ADDR 0x00000402
205 #define MSR_IA32_MC0_MISC 0x00000403
207 /* C-state Residency Counters */
208 #define MSR_PKG_C3_RESIDENCY 0x000003f8
209 #define MSR_PKG_C6_RESIDENCY 0x000003f9
210 #define MSR_PKG_C7_RESIDENCY 0x000003fa
211 #define MSR_CORE_C3_RESIDENCY 0x000003fc
212 #define MSR_CORE_C6_RESIDENCY 0x000003fd
213 #define MSR_CORE_C7_RESIDENCY 0x000003fe
214 #define MSR_PKG_C2_RESIDENCY 0x0000060d
215 #define MSR_PKG_C8_RESIDENCY 0x00000630
216 #define MSR_PKG_C9_RESIDENCY 0x00000631
217 #define MSR_PKG_C10_RESIDENCY 0x00000632
219 /* Run Time Average Power Limiting (RAPL) Interface */
221 #define MSR_PKG_POWER_SKU_UNIT 0x00000606
223 #define MSR_C_STATE_LATENCY_CONTROL_0 0x60a
224 #define MSR_C_STATE_LATENCY_CONTROL_1 0x60b
225 #define MSR_C_STATE_LATENCY_CONTROL_2 0x60c
226 #define MSR_C_STATE_LATENCY_CONTROL_3 0x633
227 #define MSR_C_STATE_LATENCY_CONTROL_4 0x634
228 #define MSR_C_STATE_LATENCY_CONTROL_5 0x635
229 #define IRTL_VALID (1 << 15)
230 #define IRTL_1_NS (0 << 10)
231 #define IRTL_32_NS (1 << 10)
232 #define IRTL_1024_NS (2 << 10)
233 #define IRTL_32768_NS (3 << 10)
234 #define IRTL_1048576_NS (4 << 10)
235 #define IRTL_33554432_NS (5 << 10)
236 #define IRTL_RESPONSE_MASK (0x3ff)
238 #define MSR_PKG_POWER_LIMIT 0x00000610
239 /* long duration in low dword, short duration in high dword */
240 #define PKG_POWER_LIMIT_MASK 0x7fff
241 #define PKG_POWER_LIMIT_EN (1 << 15)
242 #define PKG_POWER_LIMIT_CLAMP (1 << 16)
243 #define PKG_POWER_LIMIT_TIME_SHIFT 17
244 #define PKG_POWER_LIMIT_TIME_MASK 0x7f
246 * For Mobile, RAPL default PL1 time window value set to 28 seconds.
247 * RAPL time window calculation defined as follows:
248 * Time Window = (float)((1+X/4)*(2*^Y), X Corresponds to [23:22],
249 * Y to [21:17] in MSR 0x610. 28 sec is equal to 0x6e.
251 #define MB_POWER_LIMIT1_TIME_DEFAULT 0x6e
253 #define MSR_PKG_ENERGY_STATUS 0x00000611
254 #define MSR_PKG_PERF_STATUS 0x00000613
255 #define MSR_PKG_POWER_SKU 0x614
257 #define MSR_DRAM_POWER_LIMIT 0x00000618
258 #define MSR_DRAM_ENERGY_STATUS 0x00000619
259 #define MSR_DRAM_PERF_STATUS 0x0000061b
260 #define MSR_DRAM_POWER_INFO 0x0000061c
262 #define MSR_PP0_POWER_LIMIT 0x00000638
263 #define MSR_PP0_ENERGY_STATUS 0x00000639
264 #define MSR_PP0_POLICY 0x0000063a
265 #define MSR_PP0_PERF_STATUS 0x0000063b
267 #define MSR_PP1_POWER_LIMIT 0x00000640
268 #define MSR_PP1_ENERGY_STATUS 0x00000641
269 #define MSR_PP1_POLICY 0x00000642
270 #define MSR_CONFIG_TDP_NOMINAL 0x00000648
271 #define MSR_TURBO_ACTIVATION_RATIO 0x0000064c
272 #define MSR_CORE_C1_RES 0x00000660
273 #define MSR_IACORE_RATIOS 0x0000066a
274 #define MSR_IACORE_TURBO_RATIOS 0x0000066c
275 #define MSR_IACORE_VIDS 0x0000066b
276 #define MSR_IACORE_TURBO_VIDS 0x0000066d
277 #define MSR_PKG_TURBO_CFG1 0x00000670
278 #define MSR_CPU_TURBO_WKLD_CFG1 0x00000671
279 #define MSR_CPU_TURBO_WKLD_CFG2 0x00000672
280 #define MSR_CPU_THERM_CFG1 0x00000673
281 #define MSR_CPU_THERM_CFG2 0x00000674
282 #define MSR_CPU_THERM_SENS_CFG 0x00000675
284 #define MSR_AMD64_MC0_MASK 0xc0010044
286 #define MSR_IA32_MCx_CTL(x) (MSR_IA32_MC0_CTL + 4*(x))
287 #define MSR_IA32_MCx_STATUS(x) (MSR_IA32_MC0_STATUS + 4*(x))
288 #define MSR_IA32_MCx_ADDR(x) (MSR_IA32_MC0_ADDR + 4*(x))
289 #define MSR_IA32_MCx_MISC(x) (MSR_IA32_MC0_MISC + 4*(x))
291 #define MSR_AMD64_MCx_MASK(x) (MSR_AMD64_MC0_MASK + (x))
293 /* These are consecutive and not in the normal 4er MCE bank block */
294 #define MSR_IA32_MC0_CTL2 0x00000280
295 #define MSR_IA32_MCx_CTL2(x) (MSR_IA32_MC0_CTL2 + (x))
297 #define MSR_P6_PERFCTR0 0x000000c1
298 #define MSR_P6_PERFCTR1 0x000000c2
299 #define MSR_P6_EVNTSEL0 0x00000186
300 #define MSR_P6_EVNTSEL1 0x00000187
302 #define MSR_KNC_PERFCTR0 0x00000020
303 #define MSR_KNC_PERFCTR1 0x00000021
304 #define MSR_KNC_EVNTSEL0 0x00000028
305 #define MSR_KNC_EVNTSEL1 0x00000029
307 /* Alternative perfctr range with full access. */
308 #define MSR_IA32_PMC0 0x000004c1
310 /* AMD64 MSRs. Not complete. See the architecture manual for a more
313 #define MSR_AMD64_PATCH_LEVEL 0x0000008b
314 #define MSR_AMD64_TSC_RATIO 0xc0000104
315 #define MSR_AMD64_NB_CFG 0xc001001f
316 #define MSR_AMD64_PATCH_LOADER 0xc0010020
317 #define MSR_AMD64_OSVW_ID_LENGTH 0xc0010140
318 #define MSR_AMD64_OSVW_STATUS 0xc0010141
319 #define MSR_AMD64_LS_CFG 0xc0011020
320 #define MSR_AMD64_DC_CFG 0xc0011022
321 #define MSR_AMD64_BU_CFG2 0xc001102a
322 #define MSR_AMD64_IBSFETCHCTL 0xc0011030
323 #define MSR_AMD64_IBSFETCHLINAD 0xc0011031
324 #define MSR_AMD64_IBSFETCHPHYSAD 0xc0011032
325 #define MSR_AMD64_IBSFETCH_REG_COUNT 3
326 #define MSR_AMD64_IBSFETCH_REG_MASK ((1UL<<MSR_AMD64_IBSFETCH_REG_COUNT)-1)
327 #define MSR_AMD64_IBSOPCTL 0xc0011033
328 #define MSR_AMD64_IBSOPRIP 0xc0011034
329 #define MSR_AMD64_IBSOPDATA 0xc0011035
330 #define MSR_AMD64_IBSOPDATA2 0xc0011036
331 #define MSR_AMD64_IBSOPDATA3 0xc0011037
332 #define MSR_AMD64_IBSDCLINAD 0xc0011038
333 #define MSR_AMD64_IBSDCPHYSAD 0xc0011039
334 #define MSR_AMD64_IBSOP_REG_COUNT 7
335 #define MSR_AMD64_IBSOP_REG_MASK ((1UL<<MSR_AMD64_IBSOP_REG_COUNT)-1)
336 #define MSR_AMD64_IBSCTL 0xc001103a
337 #define MSR_AMD64_IBSBRTARGET 0xc001103b
338 #define MSR_AMD64_IBS_REG_COUNT_MAX 8 /* includes MSR_AMD64_IBSBRTARGET */
341 #define MSR_F16H_L2I_PERF_CTL 0xc0010230
342 #define MSR_F16H_L2I_PERF_CTR 0xc0010231
345 #define MSR_F15H_PERF_CTL 0xc0010200
346 #define MSR_F15H_PERF_CTR 0xc0010201
347 #define MSR_F15H_NB_PERF_CTL 0xc0010240
348 #define MSR_F15H_NB_PERF_CTR 0xc0010241
351 #define MSR_FAM10H_MMIO_CONF_BASE 0xc0010058
352 #define FAM10H_MMIO_CONF_ENABLE (1<<0)
353 #define FAM10H_MMIO_CONF_BUSRANGE_MASK 0xf
354 #define FAM10H_MMIO_CONF_BUSRANGE_SHIFT 2
355 #define FAM10H_MMIO_CONF_BASE_MASK 0xfffffffULL
356 #define FAM10H_MMIO_CONF_BASE_SHIFT 20
357 #define MSR_FAM10H_NODE_ID 0xc001100c
360 #define MSR_K8_TOP_MEM1 0xc001001a
361 #define MSR_K8_TOP_MEM2 0xc001001d
362 #define MSR_K8_SYSCFG 0xc0010010
363 #define MSR_K8_INT_PENDING_MSG 0xc0010055
364 /* C1E active bits in int pending message */
365 #define K8_INTP_C1E_ACTIVE_MASK 0x18000000
366 #define MSR_K8_TSEG_ADDR 0xc0010112
367 #define K8_MTRRFIXRANGE_DRAM_ENABLE 0x00040000 /* MtrrFixDramEn bit */
368 #define K8_MTRRFIXRANGE_DRAM_MODIFY 0x00080000 /* MtrrFixDramModEn bit */
369 #define K8_MTRR_RDMEM_WRMEM_MASK 0x18181818 /* Mask: RdMem|WrMem */
372 #define MSR_K7_EVNTSEL0 0xc0010000
373 #define MSR_K7_PERFCTR0 0xc0010004
374 #define MSR_K7_EVNTSEL1 0xc0010001
375 #define MSR_K7_PERFCTR1 0xc0010005
376 #define MSR_K7_EVNTSEL2 0xc0010002
377 #define MSR_K7_PERFCTR2 0xc0010006
378 #define MSR_K7_EVNTSEL3 0xc0010003
379 #define MSR_K7_PERFCTR3 0xc0010007
380 #define MSR_K7_CLK_CTL 0xc001001b
381 #define MSR_K7_HWCR 0xc0010015
382 #define MSR_K7_FID_VID_CTL 0xc0010041
383 #define MSR_K7_FID_VID_STATUS 0xc0010042
386 #define MSR_K6_WHCR 0xc0000082
387 #define MSR_K6_UWCCR 0xc0000085
388 #define MSR_K6_EPMR 0xc0000086
389 #define MSR_K6_PSOR 0xc0000087
390 #define MSR_K6_PFIR 0xc0000088
392 /* Centaur-Hauls/IDT defined MSRs. */
393 #define MSR_IDT_FCR1 0x00000107
394 #define MSR_IDT_FCR2 0x00000108
395 #define MSR_IDT_FCR3 0x00000109
396 #define MSR_IDT_FCR4 0x0000010a
398 #define MSR_IDT_MCR0 0x00000110
399 #define MSR_IDT_MCR1 0x00000111
400 #define MSR_IDT_MCR2 0x00000112
401 #define MSR_IDT_MCR3 0x00000113
402 #define MSR_IDT_MCR4 0x00000114
403 #define MSR_IDT_MCR5 0x00000115
404 #define MSR_IDT_MCR6 0x00000116
405 #define MSR_IDT_MCR7 0x00000117
406 #define MSR_IDT_MCR_CTRL 0x00000120
408 /* VIA Cyrix defined MSRs*/
409 #define MSR_VIA_FCR 0x00001107
410 #define MSR_VIA_LONGHAUL 0x0000110a
411 #define MSR_VIA_RNG 0x0000110b
412 #define MSR_VIA_BCR2 0x00001147
414 /* Transmeta defined MSRs */
415 #define MSR_TMTA_LONGRUN_CTRL 0x80868010
416 #define MSR_TMTA_LONGRUN_FLAGS 0x80868011
417 #define MSR_TMTA_LRTI_READOUT 0x80868018
418 #define MSR_TMTA_LRTI_VOLT_MHZ 0x8086801a
420 /* Intel defined MSRs. */
421 #define MSR_IA32_P5_MC_ADDR 0x00000000
422 #define MSR_IA32_P5_MC_TYPE 0x00000001
423 #define MSR_IA32_TSC 0x00000010
424 #define MSR_IA32_PLATFORM_ID 0x00000017
425 #define MSR_IA32_EBL_CR_POWERON 0x0000002a
426 #define MSR_EBC_FREQUENCY_ID 0x0000002c
427 #define MSR_SMI_COUNT 0x00000034
428 #define MSR_IA32_FEATURE_CONTROL 0x0000003a
429 #define MSR_IA32_TSC_ADJUST 0x0000003b
431 #define FEATURE_CONTROL_LOCKED (1<<0)
432 #define FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX (1<<1)
433 #define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1<<2)
435 #define MSR_IA32_APICBASE 0x0000001b
436 #define MSR_IA32_APICBASE_BSP (1<<8)
437 #define MSR_IA32_APICBASE_ENABLE (1<<11)
438 #define MSR_IA32_APICBASE_BASE (0xfffff<<12)
440 #define MSR_IA32_TSCDEADLINE 0x000006e0
442 #define MSR_IA32_UCODE_WRITE 0x00000079
443 #define MSR_IA32_UCODE_REV 0x0000008b
445 #define MSR_IA32_PERF_STATUS 0x00000198
446 #define MSR_IA32_PERF_CTL 0x00000199
447 #define MSR_AMD_PSTATE_DEF_BASE 0xc0010064
448 #define MSR_AMD_PERF_STATUS 0xc0010063
449 #define MSR_AMD_PERF_CTL 0xc0010062
451 #define MSR_PMG_CST_CONFIG_CTL 0x000000e2
452 #define MSR_PMG_IO_CAPTURE_ADR 0x000000e4
453 #define MSR_IA32_MPERF 0x000000e7
454 #define MSR_IA32_APERF 0x000000e8
456 #define MSR_IA32_THERM_CONTROL 0x0000019a
457 #define MSR_IA32_THERM_INTERRUPT 0x0000019b
459 #define THERM_INT_HIGH_ENABLE (1 << 0)
460 #define THERM_INT_LOW_ENABLE (1 << 1)
461 #define THERM_INT_PLN_ENABLE (1 << 24)
463 #define MSR_IA32_THERM_STATUS 0x0000019c
465 #define THERM_STATUS_PROCHOT (1 << 0)
466 #define THERM_STATUS_POWER_LIMIT (1 << 10)
468 #define MSR_THERM2_CTL 0x0000019d
470 #define MSR_THERM2_CTL_TM_SELECT (1ULL << 16)
472 #define MSR_IA32_TSC_DEADLINE 0x000006E0
474 /* P4/Xeon+ specific */
475 #define MSR_IA32_MCG_EAX 0x00000180
476 #define MSR_IA32_MCG_EBX 0x00000181
477 #define MSR_IA32_MCG_ECX 0x00000182
478 #define MSR_IA32_MCG_EDX 0x00000183
479 #define MSR_IA32_MCG_ESI 0x00000184
480 #define MSR_IA32_MCG_EDI 0x00000185
481 #define MSR_IA32_MCG_EBP 0x00000186
482 #define MSR_IA32_MCG_ESP 0x00000187
483 #define MSR_IA32_MCG_EFLAGS 0x00000188
484 #define MSR_IA32_MCG_EIP 0x00000189
485 #define MSR_IA32_MCG_RESERVED 0x0000018a
487 /* Pentium IV performance counter MSRs */
488 #define MSR_P4_BPU_PERFCTR0 0x00000300
489 #define MSR_P4_BPU_PERFCTR1 0x00000301
490 #define MSR_P4_BPU_PERFCTR2 0x00000302
491 #define MSR_P4_BPU_PERFCTR3 0x00000303
492 #define MSR_P4_MS_PERFCTR0 0x00000304
493 #define MSR_P4_MS_PERFCTR1 0x00000305
494 #define MSR_P4_MS_PERFCTR2 0x00000306
495 #define MSR_P4_MS_PERFCTR3 0x00000307
496 #define MSR_P4_FLAME_PERFCTR0 0x00000308
497 #define MSR_P4_FLAME_PERFCTR1 0x00000309
498 #define MSR_P4_FLAME_PERFCTR2 0x0000030a
499 #define MSR_P4_FLAME_PERFCTR3 0x0000030b
500 #define MSR_P4_IQ_PERFCTR0 0x0000030c
501 #define MSR_P4_IQ_PERFCTR1 0x0000030d
502 #define MSR_P4_IQ_PERFCTR2 0x0000030e
503 #define MSR_P4_IQ_PERFCTR3 0x0000030f
504 #define MSR_P4_IQ_PERFCTR4 0x00000310
505 #define MSR_P4_IQ_PERFCTR5 0x00000311
506 #define MSR_P4_BPU_CCCR0 0x00000360
507 #define MSR_P4_BPU_CCCR1 0x00000361
508 #define MSR_P4_BPU_CCCR2 0x00000362
509 #define MSR_P4_BPU_CCCR3 0x00000363
510 #define MSR_P4_MS_CCCR0 0x00000364
511 #define MSR_P4_MS_CCCR1 0x00000365
512 #define MSR_P4_MS_CCCR2 0x00000366
513 #define MSR_P4_MS_CCCR3 0x00000367
514 #define MSR_P4_FLAME_CCCR0 0x00000368
515 #define MSR_P4_FLAME_CCCR1 0x00000369
516 #define MSR_P4_FLAME_CCCR2 0x0000036a
517 #define MSR_P4_FLAME_CCCR3 0x0000036b
518 #define MSR_P4_IQ_CCCR0 0x0000036c
519 #define MSR_P4_IQ_CCCR1 0x0000036d
520 #define MSR_P4_IQ_CCCR2 0x0000036e
521 #define MSR_P4_IQ_CCCR3 0x0000036f
522 #define MSR_P4_IQ_CCCR4 0x00000370
523 #define MSR_P4_IQ_CCCR5 0x00000371
524 #define MSR_P4_ALF_ESCR0 0x000003ca
525 #define MSR_P4_ALF_ESCR1 0x000003cb
526 #define MSR_P4_BPU_ESCR0 0x000003b2
527 #define MSR_P4_BPU_ESCR1 0x000003b3
528 #define MSR_P4_BSU_ESCR0 0x000003a0
529 #define MSR_P4_BSU_ESCR1 0x000003a1
530 #define MSR_P4_CRU_ESCR0 0x000003b8
531 #define MSR_P4_CRU_ESCR1 0x000003b9
532 #define MSR_P4_CRU_ESCR2 0x000003cc
533 #define MSR_P4_CRU_ESCR3 0x000003cd
534 #define MSR_P4_CRU_ESCR4 0x000003e0
535 #define MSR_P4_CRU_ESCR5 0x000003e1
536 #define MSR_P4_DAC_ESCR0 0x000003a8
537 #define MSR_P4_DAC_ESCR1 0x000003a9
538 #define MSR_P4_FIRM_ESCR0 0x000003a4
539 #define MSR_P4_FIRM_ESCR1 0x000003a5
540 #define MSR_P4_FLAME_ESCR0 0x000003a6
541 #define MSR_P4_FLAME_ESCR1 0x000003a7
542 #define MSR_P4_FSB_ESCR0 0x000003a2
543 #define MSR_P4_FSB_ESCR1 0x000003a3
544 #define MSR_P4_IQ_ESCR0 0x000003ba
545 #define MSR_P4_IQ_ESCR1 0x000003bb
546 #define MSR_P4_IS_ESCR0 0x000003b4
547 #define MSR_P4_IS_ESCR1 0x000003b5
548 #define MSR_P4_ITLB_ESCR0 0x000003b6
549 #define MSR_P4_ITLB_ESCR1 0x000003b7
550 #define MSR_P4_IX_ESCR0 0x000003c8
551 #define MSR_P4_IX_ESCR1 0x000003c9
552 #define MSR_P4_MOB_ESCR0 0x000003aa
553 #define MSR_P4_MOB_ESCR1 0x000003ab
554 #define MSR_P4_MS_ESCR0 0x000003c0
555 #define MSR_P4_MS_ESCR1 0x000003c1
556 #define MSR_P4_PMH_ESCR0 0x000003ac
557 #define MSR_P4_PMH_ESCR1 0x000003ad
558 #define MSR_P4_RAT_ESCR0 0x000003bc
559 #define MSR_P4_RAT_ESCR1 0x000003bd
560 #define MSR_P4_SAAT_ESCR0 0x000003ae
561 #define MSR_P4_SAAT_ESCR1 0x000003af
562 #define MSR_P4_SSU_ESCR0 0x000003be
563 #define MSR_P4_SSU_ESCR1 0x000003bf /* guess: not in manual */
565 #define MSR_P4_TBPU_ESCR0 0x000003c2
566 #define MSR_P4_TBPU_ESCR1 0x000003c3
567 #define MSR_P4_TC_ESCR0 0x000003c4
568 #define MSR_P4_TC_ESCR1 0x000003c5
569 #define MSR_P4_U2L_ESCR0 0x000003b0
570 #define MSR_P4_U2L_ESCR1 0x000003b1
572 #define MSR_P4_PEBS_MATRIX_VERT 0x000003f2
574 /* Intel Core-based CPU performance counters */
575 #define MSR_CORE_PERF_FIXED_CTR0 0x00000309
576 #define MSR_CORE_PERF_FIXED_CTR1 0x0000030a
577 #define MSR_CORE_PERF_FIXED_CTR2 0x0000030b
578 #define MSR_CORE_PERF_FIXED_CTR_CTRL 0x0000038d
579 #define MSR_CORE_PERF_GLOBAL_STATUS 0x0000038e
580 #define MSR_CORE_PERF_GLOBAL_CTRL 0x0000038f
581 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x00000390
583 /* Geode defined MSRs */
584 #define MSR_GEODE_BUSCONT_CONF0 0x00001900
587 #define MSR_IA32_VMX_BASIC 0x00000480
588 #define MSR_IA32_VMX_PINBASED_CTLS 0x00000481
589 #define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482
590 #define MSR_IA32_VMX_EXIT_CTLS 0x00000483
591 #define MSR_IA32_VMX_ENTRY_CTLS 0x00000484
592 #define MSR_IA32_VMX_MISC 0x00000485
593 #define MSR_IA32_VMX_CR0_FIXED0 0x00000486
594 #define MSR_IA32_VMX_CR0_FIXED1 0x00000487
595 #define MSR_IA32_VMX_CR4_FIXED0 0x00000488
596 #define MSR_IA32_VMX_CR4_FIXED1 0x00000489
597 #define MSR_IA32_VMX_VMCS_ENUM 0x0000048a
598 #define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b
599 #define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c
600 #define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048d
601 #define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048e
602 #define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048f
603 #define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490
604 #define MSR_IA32_VMX_VMFUNC 0x00000491
606 #define MSR_IA32_PQR_ASSOC 0xc8f
607 /* MSR bits 33:32 encode slot number 0-3 */
608 #define MSR_IA32_PQR_ASSOC_MASK (1 << 0 | 1 << 1)
610 #define MSR_L2_QOS_MASK(reg) (0xd10 + (reg))
612 /* VMX_BASIC bits and bitmasks */
613 #define VMX_BASIC_VMCS_SIZE_SHIFT 32
614 #define VMX_BASIC_64 0x0001000000000000LLU
615 #define VMX_BASIC_MEM_TYPE_SHIFT 50
616 #define VMX_BASIC_MEM_TYPE_MASK 0x003c000000000000LLU
617 #define VMX_BASIC_MEM_TYPE_WB 6LLU
618 #define VMX_BASIC_INOUT 0x0040000000000000LLU
620 /* MSR_IA32_VMX_MISC bits */
621 #define MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS (1ULL << 29)
622 #define MSR_IA32_VMX_MISC_PREEMPTION_TIMER_SCALE 0x1F
625 #define MSR_VM_CR 0xc0010114
626 #define MSR_VM_IGNNE 0xc0010115
627 #define MSR_VM_HSAVE_PA 0xc0010117
629 #endif /* _ASM_X86_MSR_INDEX_H */