1 /* SPDX-License-Identifier: GPL-2.0 */
3 * From Coreboot src/southbridge/intel/bd82x6x/me.h
5 * Coreboot copies lots of code around. Here we are trying to keep the common
6 * code in a separate file to reduce code duplication and hopefully make it
7 * easier to add new platform.
9 * Copyright (C) 2016 Google, Inc
12 #ifndef __ASM_ME_COMMON_H
13 #define __ASM_ME_COMMON_H
15 #include <linux/compiler.h>
16 #include <linux/types.h>
19 #define MCHBAR_PEI_VERSION 0x5034
21 #define ME_RETRY 100000 /* 1 second */
22 #define ME_DELAY 10 /* 10 us */
25 * Management Engine PCI registers
28 #define PCI_CPU_MEBASE_L 0x70 /* Set by MRC */
29 #define PCI_CPU_MEBASE_H 0x74 /* Set by MRC */
31 #define PCI_ME_HFS 0x40
32 #define ME_HFS_CWS_RESET 0
33 #define ME_HFS_CWS_INIT 1
34 #define ME_HFS_CWS_REC 2
35 #define ME_HFS_CWS_NORMAL 5
36 #define ME_HFS_CWS_WAIT 6
37 #define ME_HFS_CWS_TRANS 7
38 #define ME_HFS_CWS_INVALID 8
39 #define ME_HFS_STATE_PREBOOT 0
40 #define ME_HFS_STATE_M0_UMA 1
41 #define ME_HFS_STATE_M3 4
42 #define ME_HFS_STATE_M0 5
43 #define ME_HFS_STATE_BRINGUP 6
44 #define ME_HFS_STATE_ERROR 7
45 #define ME_HFS_ERROR_NONE 0
46 #define ME_HFS_ERROR_UNCAT 1
47 #define ME_HFS_ERROR_IMAGE 3
48 #define ME_HFS_ERROR_DEBUG 4
49 #define ME_HFS_MODE_NORMAL 0
50 #define ME_HFS_MODE_DEBUG 2
51 #define ME_HFS_MODE_DIS 3
52 #define ME_HFS_MODE_OVER_JMPR 4
53 #define ME_HFS_MODE_OVER_MEI 5
54 #define ME_HFS_BIOS_DRAM_ACK 1
55 #define ME_HFS_ACK_NO_DID 0
56 #define ME_HFS_ACK_RESET 1
57 #define ME_HFS_ACK_PWR_CYCLE 2
58 #define ME_HFS_ACK_S3 3
59 #define ME_HFS_ACK_S4 4
60 #define ME_HFS_ACK_S5 5
61 #define ME_HFS_ACK_GBL_RESET 6
62 #define ME_HFS_ACK_CONTINUE 7
68 u32 operation_state:3;
69 u32 fw_init_complete:1;
71 u32 update_in_progress:1;
75 u32 boot_options_present:1;
80 #define PCI_ME_UMA 0x44
90 #define PCI_ME_H_GS 0x4c
91 #define ME_INIT_DONE 1
92 #define ME_INIT_STATUS_SUCCESS 0
93 #define ME_INIT_STATUS_NOMEM 1
94 #define ME_INIT_STATUS_ERROR 2
99 u32 rapid_start:1; /* Broadwell only */
104 #define PCI_ME_GMES 0x48
105 #define ME_GMES_PHASE_ROM 0
106 #define ME_GMES_PHASE_BUP 1
107 #define ME_GMES_PHASE_UKERNEL 2
108 #define ME_GMES_PHASE_POLICY 3
109 #define ME_GMES_PHASE_MODULE 4
110 #define ME_GMES_PHASE_UNKNOWN 5
111 #define ME_GMES_PHASE_HOST 6
117 u32 cpu_replaced_sts:1;
120 u32 warm_rst_req_for_df:1;
121 u32 cpu_replaced_valid:1;
126 u32 current_pmevent:4;
130 #define PCI_ME_HERES 0xbc
131 #define PCI_ME_EXT_SHA1 0x00
132 #define PCI_ME_EXT_SHA256 0x02
133 #define PCI_ME_HER(x) (0xc0+(4*(x)))
136 u32 extend_reg_algorithm:4;
138 u32 extend_feature_present:1;
139 u32 extend_reg_valid:1;
143 * Management Engine MEI registers
146 #define MEI_H_CB_WW 0x00
147 #define MEI_H_CSR 0x04
148 #define MEI_ME_CB_RW 0x08
149 #define MEI_ME_CSR_HA 0x0c
152 u32 interrupt_enable:1;
153 u32 interrupt_status:1;
154 u32 interrupt_generate:1;
158 u32 buffer_read_ptr:8;
159 u32 buffer_write_ptr:8;
163 #define MEI_ADDRESS_CORE 0x01
164 #define MEI_ADDRESS_AMT 0x02
165 #define MEI_ADDRESS_RESERVED 0x03
166 #define MEI_ADDRESS_WDT 0x04
167 #define MEI_ADDRESS_MKHI 0x07
168 #define MEI_ADDRESS_ICC 0x08
169 #define MEI_ADDRESS_THERMAL 0x09
171 #define MEI_HOST_ADDRESS 0
174 u32 client_address:8;
181 #define MKHI_GROUP_ID_CBM 0x00
182 #define MKHI_GROUP_ID_FWCAPS 0x03
183 #define MKHI_GROUP_ID_MDES 0x08
184 #define MKHI_GROUP_ID_GEN 0xff
186 #define MKHI_GET_FW_VERSION 0x02
187 #define MKHI_END_OF_POST 0x0c
188 #define MKHI_FEATURE_OVERRIDE 0x14
190 /* Ivybridge only: */
191 #define MKHI_GLOBAL_RESET 0x0b
192 #define MKHI_FWCAPS_GET_RULE 0x02
193 #define MKHI_MDES_ENABLE 0x09
195 /* Broadwell only: */
196 #define MKHI_GLOBAL_RESET 0x0b
197 #define MKHI_FWCAPS_GET_RULE 0x02
198 #define MKHI_GROUP_ID_HMRFPO 0x05
199 #define MKHI_HMRFPO_LOCK 0x02
200 #define MKHI_HMRFPO_LOCK_NOACK 0x05
201 #define MKHI_MDES_ENABLE 0x09
202 #define MKHI_END_OF_POST_NOACK 0x1a
212 struct me_fw_version {
215 u16 code_build_number;
219 u16 recovery_build_number;
220 u16 recovery_hot_fix;
224 #define HECI_EOP_STATUS_SUCCESS 0x0
225 #define HECI_EOP_PERFORM_GLOBAL_RESET 0x1
227 #define CBM_RR_GLOBAL_RESET 0x01
229 #define GLOBAL_RESET_BIOS_MRC 0x01
230 #define GLOBAL_RESET_BIOS_POST 0x02
231 #define GLOBAL_RESET_MEBX 0x03
233 struct me_global_reset {
242 ME_RECOVERY_BIOS_PATH,
243 ME_DISABLE_BIOS_PATH,
244 ME_FIRMWARE_UPDATE_BIOS_PATH,
247 struct __packed mefwcaps_sku {
251 u32 small_business:1;
252 u32 l3manageability:1;
257 u32 icc_over_clocking:1;
270 struct __packed tdt_state_flag {
272 u16 authenticate_module:1;
273 u16 s3authentication:1;
274 u16 flash_wear_out:1;
275 u16 flash_variable_security:1;
276 u16 wwan3gpresent:1; /* ivybridge only */
277 u16 wwan3goob:1; /* ivybridge only */
281 struct __packed tdt_state_info {
283 u8 last_theft_trigger;
284 struct tdt_state_flag flags;
287 struct __packed mbp_rom_bist_data {
293 struct __packed mbp_platform_key {
297 struct __packed mbp_header {
303 struct __packed mbp_item_header {
310 struct __packed me_fwcaps {
313 struct mefwcaps_sku caps_sku;
318 * intel_me_status() - Check Intel Management Engine status
320 * @me_dev: Management engine PCI device
322 void intel_me_status(struct udevice *me_dev);
325 * intel_early_me_init() - Early Intel Management Engine init
327 * @me_dev: Management engine PCI device
328 * @return 0 if OK, -ve on error
330 int intel_early_me_init(struct udevice *me_dev);
333 * intel_early_me_uma_size() - Get UMA size from the Intel Management Engine
335 * @me_dev: Management engine PCI device
336 * @return UMA size if OK, -EINVAL on error
338 int intel_early_me_uma_size(struct udevice *me_dev);
341 * intel_early_me_init_done() - Complete Intel Management Engine init
343 * @dev: Northbridge device
344 * @me_dev: Management engine PCI device
345 * @status: Status result (ME_INIT_...)
346 * @return 0 to continue to boot, -EINVAL on unknown result data, -ETIMEDOUT
347 * if ME did not respond
349 int intel_early_me_init_done(struct udevice *dev, struct udevice *me_dev,
352 int intel_me_hsio_version(struct udevice *dev, uint16_t *version,
355 static inline void pci_read_dword_ptr(struct udevice *me_dev, void *ptr,
360 dm_pci_read_config32(me_dev, offset, &dword);
361 memcpy(ptr, &dword, sizeof(dword));
364 static inline void pci_write_dword_ptr(struct udevice *me_dev, void *ptr,
369 memcpy(&dword, ptr, sizeof(dword));
370 dm_pci_write_config32(me_dev, offset, dword);