2 * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <dt-bindings/interrupt-router/intel-irq.h>
13 * Intel interrupt router configuration mechanism
15 * There are two known ways of Intel interrupt router configuration mechanism
16 * so far. On most cases, the IRQ routing configuraiton is controlled by PCI
17 * configuraiton registers on the legacy bridge, normally PCI BDF(0, 31, 0).
18 * On some newer platforms like BayTrail and Braswell, the IRQ routing is now
19 * in the IBASE register block where IBASE is memory-mapped.
27 * Intel interrupt router control block
29 * Its members' value will be filled in based on device tree's input.
31 * @config: PIRQ_VIA_PCI or PIRQ_VIA_IBASE
32 * @link_base: link value base number
33 * @irq_mask: IRQ mask reprenting the 16 IRQs in 8259, bit N is 1 means
34 * IRQ N is available to be routed
35 * @lb_bdf: irq router's PCI bus/device/function number encoding
36 * @ibase: IBASE register block base address
52 /* PIRQ link number and value conversion */
53 #define LINK_V2N(link, base) (link - base)
54 #define LINK_N2V(link, base) (link + base)
56 #define PIRQ_BITMAP 0xdef8
59 * cpu_irq_init() - Initialize CPU IRQ routing
61 * This initializes some platform-specific registers related to IRQ routing,
62 * like configuring internal PCI devices to use which PCI interrupt pin,
63 * and which PCI interrupt pin is mapped to which PIRQ line. Note on some
64 * platforms, such IRQ routing might be hard-coded thus cannot configure.
66 void cpu_irq_init(void);
69 * pirq_init() - Initialize platform PIRQ routing
71 * This initializes the PIRQ routing on the platform and configures all PCI
72 * devices' interrupt line register to a working IRQ number on the 8259 PIC.
76 #endif /* _ARCH_IRQ_H_ */