2 * From coreboot file of the same name
4 * Copyright (C) 2010 coresystems GmbH
6 * SPDX-License-Identifier: GPL-2.0
10 #define __ASM_IOAPIC_H
12 #define IO_APIC_ADDR 0xfec00000
13 #define IO_APIC_INDEX IO_APIC_ADDR
14 #define IO_APIC_DATA (IO_APIC_ADDR + 0x10)
15 #define IO_APIC_INTERRUPTS 24
17 #define ALL (0xff << 24)
19 #define DISABLED (1 << 16)
20 #define ENABLED (0 << 16)
21 #define TRIGGER_EDGE (0 << 15)
22 #define TRIGGER_LEVEL (1 << 15)
23 #define POLARITY_HIGH (0 << 13)
24 #define POLARITY_LOW (1 << 13)
25 #define PHYSICAL_DEST (0 << 11)
26 #define LOGICAL_DEST (1 << 11)
27 #define ExtINT (7 << 8)
32 u32 io_apic_read(u32 ioapic_base, u32 reg);
33 void io_apic_write(u32 ioapic_base, u32 reg, u32 value);
34 void set_ioapic_id(u32 ioapic_base, u8 ioapic_id);
35 void setup_ioapic(u32 ioapic_base, u8 ioapic_id);
36 void clear_ioapic(u32 ioapic_base);