1 /* SPDX-License-Identifier: GPL-2.0 */
3 * This file is part of the coreboot project.
5 * Copyright (C) 2015-2016 Intel Corp.
6 * Copyright 2019 Google LLC
8 * Modified from coreboot gpio_defs.h
11 #ifndef _ASM_INTEL_PINCTRL_DEFS_H_
12 #define _ASM_INTEL_PINCTRL_DEFS_H_
14 /* This file is included by device trees, so avoid BIT() macros */
16 #define PAD_CFG0_TX_STATE_BIT 0
17 #define PAD_CFG0_TX_STATE (1 << PAD_CFG0_TX_STATE_BIT)
18 #define PAD_CFG0_RX_STATE_BIT 1
19 #define PAD_CFG0_RX_STATE (1 << PAD_CFG0_RX_STATE_BIT)
20 #define PAD_CFG0_TX_DISABLE (1 << 8)
21 #define PAD_CFG0_RX_DISABLE (1 << 9)
23 #define PAD_CFG0_MODE_SHIFT 10
24 #define PAD_CFG0_MODE_MASK (7 << PAD_CFG0_MODE_SHIFT)
25 #define PAD_CFG0_MODE_GPIO (0 << PAD_CFG0_MODE_SHIFT)
26 #define PAD_CFG0_MODE_NF1 (1 << PAD_CFG0_MODE_SHIFT)
27 #define PAD_CFG0_MODE_NF2 (2 << PAD_CFG0_MODE_SHIFT)
28 #define PAD_CFG0_MODE_NF3 (3 << PAD_CFG0_MODE_SHIFT)
29 #define PAD_CFG0_MODE_NF4 (4 << PAD_CFG0_MODE_SHIFT)
30 #define PAD_CFG0_MODE_NF5 (5 << PAD_CFG0_MODE_SHIFT)
31 #define PAD_CFG0_MODE_NF6 (6 << PAD_CFG0_MODE_SHIFT)
33 #define PAD_CFG0_ROUTE_MASK (0xf << 17)
34 #define PAD_CFG0_ROUTE_NMI (1 << 17)
35 #define PAD_CFG0_ROUTE_SMI (1 << 18)
36 #define PAD_CFG0_ROUTE_SCI (1 << 19)
37 #define PAD_CFG0_ROUTE_IOAPIC (1 << 20)
38 #define PAD_CFG0_RXTENCFG_MASK (3 << 21)
39 #define PAD_CFG0_RXINV_MASK (1 << 23)
40 #define PAD_CFG0_RX_POL_INVERT (1 << 23)
41 #define PAD_CFG0_RX_POL_NONE (0 << 23)
42 #define PAD_CFG0_PREGFRXSEL (1 << 24)
43 #define PAD_CFG0_TRIG_MASK (3 << 25)
44 #define PAD_CFG0_TRIG_LEVEL (0 << 25)
45 #define PAD_CFG0_TRIG_EDGE_SINGLE (1 << 25) /* controlled by RX_INVERT*/
46 #define PAD_CFG0_TRIG_OFF (2 << 25)
47 #define PAD_CFG0_TRIG_EDGE_BOTH (3 << 25)
48 #define PAD_CFG0_RXRAW1_MASK (1 << 28)
49 #define PAD_CFG0_RXPADSTSEL_MASK (1 << 29)
50 #define PAD_CFG0_RESET_MASK (3 << 30)
51 #define PAD_CFG0_LOGICAL_RESET_PWROK (0U << 30)
52 #define PAD_CFG0_LOGICAL_RESET_DEEP (1U << 30)
53 #define PAD_CFG0_LOGICAL_RESET_PLTRST (2U << 30)
54 #define PAD_CFG0_LOGICAL_RESET_RSMRST (3U << 30)
57 * Use the fourth bit in IntSel field to indicate gpio ownership. This field is
58 * RO and hence not used during gpio configuration.
60 #define PAD_CFG1_GPIO_DRIVER (0x1 << 4)
61 #define PAD_CFG1_IRQ_MASK (0xff << 0)
62 #define PAD_CFG1_IOSTERM_MASK (0x3 << 8)
63 #define PAD_CFG1_IOSTERM_SAME (0x0 << 8)
64 #define PAD_CFG1_IOSTERM_DISPUPD (0x1 << 8)
65 #define PAD_CFG1_IOSTERM_ENPD (0x2 << 8)
66 #define PAD_CFG1_IOSTERM_ENPU (0x3 << 8)
67 #define PAD_CFG1_PULL_MASK (0xf << 10)
68 #define PAD_CFG1_PULL_NONE (0x0 << 10)
69 #define PAD_CFG1_PULL_DN_5K (0x2 << 10)
70 #define PAD_CFG1_PULL_DN_20K (0x4 << 10)
71 #define PAD_CFG1_PULL_UP_1K (0x9 << 10)
72 #define PAD_CFG1_PULL_UP_5K (0xa << 10)
73 #define PAD_CFG1_PULL_UP_2K (0xb << 10)
74 #define PAD_CFG1_PULL_UP_20K (0xc << 10)
75 #define PAD_CFG1_PULL_UP_667 (0xd << 10)
76 #define PAD_CFG1_PULL_NATIVE (0xf << 10)
78 /* Tx enabled driving last value driven, Rx enabled */
79 #define PAD_CFG1_IOSSTATE_TX_LAST_RXE (0x0 << 14)
81 * Tx enabled driving 0, Rx disabled and Rx driving 0 back to its controller
84 #define PAD_CFG1_IOSSTATE_TX0_RX_DCR_X0 (0x1 << 14)
86 * Tx enabled driving 0, Rx disabled and Rx driving 1 back to its controller
89 #define PAD_CFG1_IOSSTATE_TX0_RX_DCR_X1 (0x2 << 14)
91 * Tx enabled driving 1, Rx disabled and Rx driving 0 back to its controller
94 #define PAD_CFG1_IOSSTATE_TX1_RX_DCR_X0 (0x3 << 14)
96 * Tx enabled driving 1, Rx disabled and Rx driving 1 back to its controller
99 #define PAD_CFG1_IOSSTATE_TX1_RX_DCR_X1 (0x4 << 14)
100 /* Tx enabled driving 0, Rx enabled */
101 #define PAD_CFG1_IOSSTATE_TX0_RXE (0x5 << 14)
102 /* Tx enabled driving 1, Rx enabled */
103 #define PAD_CFG1_IOSSTATE_TX1_RXE (0x6 << 14)
104 /* Hi-Z, Rx driving 0 back to its controller internally */
105 #define PAD_CFG1_IOSSTATE_HIZCRX0 (0x7 << 14)
106 /* Hi-Z, Rx driving 1 back to its controller internally */
107 #define PAD_CFG1_IOSSTATE_HIZCRX1 (0x8 << 14)
108 /* Tx disabled, Rx enabled */
109 #define PAD_CFG1_IOSSTATE_TXD_RXE (0x9 << 14)
110 #define PAD_CFG1_IOSSTATE_IGNORE (0xf << 14) /* Ignore Iostandby */
111 /* mask to extract Iostandby bits */
112 #define PAD_CFG1_IOSSTATE_MASK (0xf << 14)
113 #define PAD_CFG1_IOSSTATE_SHIFT 14 /* set Iostandby bits [17:14] */
115 #define PAD_CFG2_DEBEN 1
116 /* Debounce Duration = (2 ^ PAD_CFG2_DEBOUNCE_x_RTC) * RTC clock duration */
117 #define PAD_CFG2_DEBOUNCE_8_RTC (0x3 << 1)
118 #define PAD_CFG2_DEBOUNCE_16_RTC (0x4 << 1)
119 #define PAD_CFG2_DEBOUNCE_32_RTC (0x5 << 1)
120 #define PAD_CFG2_DEBOUNCE_64_RTC (0x6 << 1)
121 #define PAD_CFG2_DEBOUNCE_128_RTC (0x7 << 1)
122 #define PAD_CFG2_DEBOUNCE_256_RTC (0x8 << 1)
123 #define PAD_CFG2_DEBOUNCE_512_RTC (0x9 << 1)
124 #define PAD_CFG2_DEBOUNCE_1K_RTC (0xa << 1)
125 #define PAD_CFG2_DEBOUNCE_2K_RTC (0xb << 1)
126 #define PAD_CFG2_DEBOUNCE_4K_RTC (0xc << 1)
127 #define PAD_CFG2_DEBOUNCE_8K_RTC (0xd << 1)
128 #define PAD_CFG2_DEBOUNCE_16K_RTC (0xe << 1)
129 #define PAD_CFG2_DEBOUNCE_32K_RTC (0xf << 1)
130 #define PAD_CFG2_DEBOUNCE_MASK 0x1f
132 /* voltage tolerance 0=3.3V default 1=1.8V tolerant */
133 #if IS_ENABLED(INTEL_PINCTRL_IOSTANDBY)
134 #define PAD_CFG1_TOL_MASK (0x1 << 25)
135 #define PAD_CFG1_TOL_1V8 (0x1 << 25)
138 #define PAD_FUNC(value) PAD_CFG0_MODE_##value
139 #define PAD_RESET(value) PAD_CFG0_LOGICAL_RESET_##value
140 #define PAD_PULL(value) PAD_CFG1_PULL_##value
142 #define PAD_IOSSTATE(value) PAD_CFG1_IOSSTATE_##value
143 #define PAD_IOSTERM(value) PAD_CFG1_IOSTERM_##value
145 #define PAD_IRQ_CFG(route, trig, inv) \
146 (PAD_CFG0_ROUTE_##route | \
147 PAD_CFG0_TRIG_##trig | \
148 PAD_CFG0_RX_POL_##inv)
150 #if IS_ENABLED(INTEL_PINCTRL_DUAL_ROUTE_SUPPORT)
151 #define PAD_IRQ_CFG_DUAL_ROUTE(route1, route2, trig, inv) \
152 (PAD_CFG0_ROUTE_##route1 | \
153 PAD_CFG0_ROUTE_##route2 | \
154 PAD_CFG0_TRIG_##trig | \
155 PAD_CFG0_RX_POL_##inv)
156 #endif /* CONFIG_INTEL_PINCTRL_DUAL_ROUTE_SUPPORT */
158 #define _PAD_CFG_STRUCT(__pad, __config0, __config1) \
159 __pad(__config0) (__config1)
161 /* Native function configuration */
162 #define PAD_CFG_NF(pad, pull, rst, func) \
163 _PAD_CFG_STRUCT(pad, PAD_RESET(rst) | PAD_FUNC(func), PAD_PULL(pull) | \
164 PAD_IOSSTATE(TX_LAST_RXE))
166 #if IS_ENABLED(CONFIG_INTEL_GPIO_PADCFG_PADTOL)
168 * Native 1.8V tolerant pad, only applies to some pads like I2C/I2S. Not
169 * applicable to all SOCs. Refer EDS.
171 #define PAD_CFG_NF_1V8(pad, pull, rst, func) \
172 _PAD_CFG_STRUCT(pad, PAD_RESET(rst) | PAD_FUNC(func), PAD_PULL(pull) |\
173 PAD_IOSSTATE(TX_LAST_RXE) | PAD_CFG1_TOL_1V8)
176 /* Native function configuration for standby state */
177 #define PAD_CFG_NF_IOSSTATE(pad, pull, rst, func, iosstate) \
178 _PAD_CFG_STRUCT(pad, PAD_RESET(rst) | PAD_FUNC(func), PAD_PULL(pull) | \
179 PAD_IOSSTATE(iosstate))
182 * Native function configuration for standby state, also configuring iostandby
185 #define PAD_CFG_NF_IOSTANDBY_IGNORE(pad, pull, rst, func) \
186 _PAD_CFG_STRUCT(pad, PAD_RESET(rst) | PAD_FUNC(func), PAD_PULL(pull) | \
187 PAD_IOSSTATE(IGNORE))
190 * Native function configuration for standby state, also configuring iosstate
193 #define PAD_CFG_NF_IOSSTATE_IOSTERM(pad, pull, rst, func, iosstate, iosterm) \
194 _PAD_CFG_STRUCT(pad, PAD_RESET(rst) | PAD_FUNC(func), PAD_PULL(pull) | \
195 PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm))
197 /* General purpose output, no pullup/down */
198 #define PAD_CFG_GPO(pad, val, rst) \
199 _PAD_CFG_STRUCT(pad, \
200 PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_RX_DISABLE | !!val, \
201 PAD_PULL(NONE) | PAD_IOSSTATE(TX_LAST_RXE))
203 /* General purpose output, with termination specified */
204 #define PAD_CFG_TERM_GPO(pad, val, pull, rst) \
205 _PAD_CFG_STRUCT(pad, \
206 PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_RX_DISABLE | !!val, \
207 PAD_PULL(pull) | PAD_IOSSTATE(TX_LAST_RXE))
209 /* General purpose output, no pullup/down */
210 #define PAD_CFG_GPO_GPIO_DRIVER(pad, val, rst, pull) \
211 _PAD_CFG_STRUCT(pad, \
212 PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_RX_DISABLE | !!val, \
213 PAD_PULL(pull) | PAD_IOSSTATE(TX_LAST_RXE) | \
214 PAD_CFG1_GPIO_DRIVER)
216 /* General purpose output */
217 #define PAD_CFG_GPO_IOSSTATE_IOSTERM(pad, val, rst, pull, iosstate, ioterm) \
218 _PAD_CFG_STRUCT(pad, \
219 PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_RX_DISABLE | !!val, \
220 PAD_PULL(pull) | PAD_IOSSTATE(iosstate) | PAD_IOSTERM(ioterm))
222 /* General purpose input */
223 #define PAD_CFG_GPI(pad, pull, rst) \
224 _PAD_CFG_STRUCT(pad, \
225 PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE, \
226 PAD_PULL(pull) | PAD_IOSSTATE(TXD_RXE))
228 /* General purpose input. The following macro sets the
229 * Host Software Pad Ownership to GPIO Driver mode.
231 #define PAD_CFG_GPI_GPIO_DRIVER(pad, pull, rst) \
232 _PAD_CFG_STRUCT(pad, \
233 PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE, \
234 PAD_PULL(pull) | PAD_CFG1_GPIO_DRIVER | PAD_IOSSTATE(TXD_RXE))
236 #define PAD_CFG_GPIO_DRIVER_HI_Z(pad, pull, rst, iosstate, iosterm) \
237 _PAD_CFG_STRUCT(pad, \
238 PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \
239 PAD_CFG0_RX_DISABLE, \
240 PAD_PULL(pull) | PAD_CFG1_GPIO_DRIVER | \
241 PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm))
243 #define PAD_CFG_GPIO_HI_Z(pad, pull, rst, iosstate, iosterm) \
244 _PAD_CFG_STRUCT(pad, \
245 PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \
246 PAD_CFG0_RX_DISABLE, PAD_PULL(pull) | \
247 PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm))
250 #define PAD_CFG_GPI_INT(pad, pull, rst, trig) \
251 _PAD_CFG_STRUCT(pad, \
252 PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \
253 PAD_CFG0_TRIG_##trig | PAD_CFG0_RX_POL_NONE, \
254 PAD_PULL(pull) | PAD_CFG1_GPIO_DRIVER | PAD_IOSSTATE(TXD_RXE))
257 * No Connect configuration for unused pad.
258 * Both TX and RX are disabled. RX disabling is done to avoid unnecessary
259 * setting of GPI_STS.
261 #define PAD_NC(pad, pull) \
262 _PAD_CFG_STRUCT(pad, \
263 PAD_FUNC(GPIO) | PAD_RESET(DEEP) | \
264 PAD_CFG0_TX_DISABLE | PAD_CFG0_RX_DISABLE, \
265 PAD_PULL(pull) | PAD_IOSSTATE(TXD_RXE))
267 /* General purpose input, routed to APIC */
268 #define PAD_CFG_GPI_APIC(pad, pull, rst, trig, inv) \
269 _PAD_CFG_STRUCT(pad, \
270 PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \
271 PAD_IRQ_CFG(IOAPIC, trig, inv), PAD_PULL(pull) | \
272 PAD_IOSSTATE(TXD_RXE))
274 /* General purpose input, routed to APIC - with IOStandby Config*/
275 #define PAD_CFG_GPI_APIC_IOS(pad, pull, rst, trig, inv, iosstate, iosterm) \
276 _PAD_CFG_STRUCT(pad, \
277 PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \
278 PAD_IRQ_CFG(IOAPIC, trig, inv), PAD_PULL(pull) | \
279 PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm))
282 * The following APIC macros assume the APIC will handle the filtering
283 * on its own end. One just needs to pass an active high message into the
286 #define PAD_CFG_GPI_APIC_LOW(pad, pull, rst) \
287 PAD_CFG_GPI_APIC(pad, pull, rst, LEVEL, INVERT)
289 #define PAD_CFG_GPI_APIC_HIGH(pad, pull, rst) \
290 PAD_CFG_GPI_APIC(pad, pull, rst, LEVEL, NONE)
292 #define PAD_CFG_GPI_APIC_EDGE_LOW(pad, pull, rst) \
293 PAD_CFG_GPI_APIC(pad, pull, rst, EDGE_SINGLE, INVERT)
295 /* General purpose input, routed to SMI */
296 #define PAD_CFG_GPI_SMI(pad, pull, rst, trig, inv) \
297 _PAD_CFG_STRUCT(pad, \
298 PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \
299 PAD_IRQ_CFG(SMI, trig, inv), PAD_PULL(pull) | \
300 PAD_IOSSTATE(TXD_RXE))
302 /* General purpose input, routed to SMI */
303 #define PAD_CFG_GPI_SMI_IOS(pad, pull, rst, trig, inv, iosstate, iosterm) \
304 _PAD_CFG_STRUCT(pad, \
305 PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \
306 PAD_IRQ_CFG(SMI, trig, inv), PAD_PULL(pull) | \
307 PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm))
309 #define PAD_CFG_GPI_SMI_LOW(pad, pull, rst, trig) \
310 PAD_CFG_GPI_SMI(pad, pull, rst, trig, INVERT)
312 #define PAD_CFG_GPI_SMI_HIGH(pad, pull, rst, trig) \
313 PAD_CFG_GPI_SMI(pad, pull, rst, trig, NONE)
315 /* General purpose input, routed to SCI */
316 #define PAD_CFG_GPI_SCI(pad, pull, rst, trig, inv) \
317 _PAD_CFG_STRUCT(pad, \
318 PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \
319 PAD_IRQ_CFG(SCI, trig, inv), PAD_PULL(pull) | \
320 PAD_IOSSTATE(TXD_RXE))
322 /* General purpose input, routed to SCI */
323 #define PAD_CFG_GPI_SCI_IOS(pad, pull, rst, trig, inv, iosstate, iosterm) \
324 _PAD_CFG_STRUCT(pad, \
325 PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \
326 PAD_IRQ_CFG(SCI, trig, inv), PAD_PULL(pull) | \
327 PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm))
329 #define PAD_CFG_GPI_SCI_LOW(pad, pull, rst, trig) \
330 PAD_CFG_GPI_SCI(pad, pull, rst, trig, INVERT)
332 #define PAD_CFG_GPI_SCI_HIGH(pad, pull, rst, trig) \
333 PAD_CFG_GPI_SCI(pad, pull, rst, trig, NONE)
335 #define PAD_CFG_GPI_SCI_DEBEN(pad, pull, rst, trig, inv, dur) \
336 _PAD_CFG_STRUCT_3(pad, \
337 PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \
338 PAD_IRQ_CFG(SCI, trig, inv), PAD_PULL(pull) | \
339 PAD_IOSSTATE(TXD_RXE), PAD_CFG2_DEBEN | PAD_CFG2_##dur)
341 #define PAD_CFG_GPI_SCI_LOW_DEBEN(pad, pull, rst, trig, dur) \
342 PAD_CFG_GPI_SCI_DEBEN(pad, pull, rst, trig, INVERT, dur)
344 #define PAD_CFG_GPI_SCI_HIGH_DEBEN(pad, pull, rst, trig, dur) \
345 PAD_CFG_GPI_SCI_DEBEN(pad, pull, rst, trig, NONE, dur)
347 /* General purpose input, routed to NMI */
348 #define PAD_CFG_GPI_NMI(pad, pull, rst, trig, inv) \
349 _PAD_CFG_STRUCT(pad, \
350 PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \
351 PAD_IRQ_CFG(NMI, trig, inv), PAD_PULL(pull) | \
352 PAD_IOSSTATE(TXD_RXE))
354 #if IS_ENABLED(INTEL_PINCTRL_DUAL_ROUTE_SUPPORT)
355 /* GPI, GPIO Driver, SCI interrupt */
356 #define PAD_CFG_GPI_GPIO_DRIVER_SCI(pad, pull, rst, trig, inv) \
357 _PAD_CFG_STRUCT(pad, \
358 PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \
359 PAD_IRQ_CFG(SCI, trig, inv), \
360 PAD_PULL(pull) | PAD_CFG1_GPIO_DRIVER | PAD_IOSSTATE(TXD_RXE))
362 #define PAD_CFG_GPI_DUAL_ROUTE(pad, pull, rst, trig, inv, route1, route2) \
363 _PAD_CFG_STRUCT(pad, \
364 PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \
365 PAD_IRQ_CFG_DUAL_ROUTE(route1, route2, trig, inv), \
366 PAD_PULL(pull) | PAD_IOSSTATE(TXD_RXE))
368 #define PAD_CFG_GPI_IRQ_WAKE(pad, pull, rst, trig, inv) \
369 PAD_CFG_GPI_DUAL_ROUTE(pad, pull, rst, trig, inv, IOAPIC, SCI)
371 #endif /* CONFIG_INTEL_PINCTRL_DUAL_ROUTE_SUPPORT */
373 #endif /* _ASM_INTEL_PINCTRL_DEFS_H_ */