1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2017 Intel Corporation.
4 * Copyright 2019 Google LLC
6 * Modified from coreboot gpio.h
9 #ifndef __ASM_INTEL_PINCTRL_H
10 #define __ASM_INTEL_PINCTRL_H
12 #include <dm/pinctrl.h>
13 #include <linux/bitops.h>
16 * struct pad_config - config for a pad
17 * @pad: offset of pad within community
18 * @pad_config: Pad config data corresponding to DW0, DW1, etc.
25 #include <asm/arch/gpio.h>
27 /* GPIO community IOSF sideband clock gating */
28 #define MISCCFG_GPSIDEDPCGEN BIT(5)
29 /* GPIO community RCOMP clock gating */
30 #define MISCCFG_GPRCOMPCDLCGEN BIT(4)
31 /* GPIO community RTC clock gating */
32 #define MISCCFG_GPRTCDLCGEN BIT(3)
33 /* GFX controller clock gating */
34 #define MISCCFG_GSXSLCGEN BIT(2)
35 /* GPIO community partition clock gating */
36 #define MISCCFG_GPDPCGEN BIT(1)
37 /* GPIO community local clock gating */
38 #define MISCCFG_GPDLCGEN BIT(0)
39 /* Enable GPIO community power management configuration */
40 #define MISCCFG_ENABLE_GPIO_PM_CONFIG (MISCCFG_GPSIDEDPCGEN | \
41 MISCCFG_GPRCOMPCDLCGEN | MISCCFG_GPRTCDLCGEN | MISCCFG_GSXSLCGEN \
42 | MISCCFG_GPDPCGEN | MISCCFG_GPDLCGEN)
45 * GPIO numbers may not be contiguous and instead will have a different
46 * starting pin number for each pad group.
48 #define INTEL_GPP_BASE(first_of_community, start_of_group, end_of_group,\
51 .first_pad = (start_of_group) - (first_of_community), \
52 .size = (end_of_group) - (start_of_group) + 1, \
53 .acpi_pad_base = (group_pad_base), \
57 * A pad base of -1 indicates that this group uses contiguous numbering
58 * and a pad base should not be used for this group.
60 #define PAD_BASE_NONE -1
62 /* The common/default group numbering is contiguous */
63 #define INTEL_GPP(first_of_community, start_of_group, end_of_group) \
64 INTEL_GPP_BASE(first_of_community, start_of_group, end_of_group,\
68 * struct reset_mapping - logical to actual value for PADRSTCFG in DW0
70 * Note that the values are expected to be within the field placement of the
71 * register itself. i.e. if the reset field is at 31:30 then the values within
72 * logical and chipset should occupy 31:30.
74 struct reset_mapping {
80 * struct pad_group - describes the groups within each community
82 * @first_pad: offset of first pad of the group relative to the community
83 * @size: size of the group
84 * @acpi_pad_base: starting pin number for the pads in this group when they are
85 * used in ACPI. This is only needed if the pins are not contiguous across
86 * groups. Most groups will have this set to PAD_BASE_NONE and use
87 * contiguous numbering for ACPI.
96 * struct pad_community - community of pads
98 * This describes a community, or each group within a community when multiple
99 * groups exist inside a community
101 * @name: Community name
102 * @acpi_path: ACPI path
103 * @num_gpi_regs: number of gpi registers in community
104 * @max_pads_per_group: number of pads in each group; number of pads bit-mapped
105 * in each GPI status/en and Host Own Reg
106 * @first_pad: first pad in community
107 * @last_pad: last pad in community
108 * @host_own_reg_0: offset to Host Ownership Reg 0
109 * @gpi_int_sts_reg_0: offset to GPI Int STS Reg 0
110 * @gpi_int_en_reg_0: offset to GPI Int Enable Reg 0
111 * @gpi_smi_sts_reg_0: offset to GPI SMI STS Reg 0
112 * @gpi_smi_en_reg_0: offset to GPI SMI EN Reg 0
113 * @pad_cfg_base: offset to first PAD_GFG_DW0 Reg
114 * @gpi_status_offset: specifies offset in struct gpi_status
116 * @reset_map: PADRSTCFG logical to chipset mapping
117 * @num_reset_vals: number of values in @reset_map
118 * @groups; list of groups for this community
119 * @num_groups: number of groups
121 struct pad_community {
123 const char *acpi_path;
125 size_t max_pads_per_group;
129 u16 gpi_int_sts_reg_0;
130 u16 gpi_int_en_reg_0;
131 u16 gpi_smi_sts_reg_0;
132 u16 gpi_smi_en_reg_0;
134 u8 gpi_status_offset;
136 const struct reset_mapping *reset_map;
137 size_t num_reset_vals;
138 const struct pad_group *groups;
143 * struct intel_pinctrl_priv - private data for each pinctrl device
145 * @comm: Pad community for this device
146 * @num_cfgs: Number of configuration words for each pad
147 * @itss: ITSS device (for interrupt handling)
148 * @itss_pol_cfg: Use to program Interrupt Polarity Control (IPCx) register
149 * Each bit represents IRQx Active High Polarity Disable configuration:
150 * when set to 1, the interrupt polarity associated with IRQx is inverted
151 * to appear as Active Low to IOAPIC and vice versa
153 struct intel_pinctrl_priv {
154 const struct pad_community *comm;
156 struct udevice *itss;
160 /* Exported common operations for the pinctrl driver */
161 extern const struct pinctrl_ops intel_pinctrl_ops;
163 /* Exported common probe function for the pinctrl driver */
164 int intel_pinctrl_probe(struct udevice *dev);
167 * intel_pinctrl_ofdata_to_platdata() - Handle common platdata setup
169 * @dev: Pinctrl device
170 * @comm: Pad community for this device
171 * @num_cfgs: Number of configuration words for each pad
172 * @return 0 if OK, -EDOM if @comm is NULL, other -ve value on other error
174 int intel_pinctrl_ofdata_to_platdata(struct udevice *dev,
175 const struct pad_community *comm,
179 * pinctrl_route_gpe() - set GPIO groups for the general-purpose-event blocks
181 * The values from PMC register GPE_CFG are passed which is then mapped to
182 * proper groups for MISCCFG. This basically sets the MISCCFG register bits:
183 * dw0 = gpe0_route[11:8]. This is ACPI GPE0b.
184 * dw1 = gpe0_route[15:12]. This is ACPI GPE0c.
185 * dw2 = gpe0_route[19:16]. This is ACPI GPE0d.
188 * @gpe0b: Value for GPE0B
189 * @gpe0c: Value for GPE0C
190 * @gpe0d: Value for GPE0D
191 * @return 0 if OK, -ve on error
193 int pinctrl_route_gpe(struct udevice *dev, uint gpe0b, uint gpe0c, uint gpe0d);
196 * pinctrl_config_pads() - Configure a list of pads
198 * Configures multiple pads using the provided data from the device tree.
200 * @dev: pinctrl device (any will do)
201 * @pads: Pad data, consisting of a pad number followed by num_cfgs entries
202 * containing the data for that pad (num_cfgs is set by the pinctrl device)
203 * @pads_count: Number of pads to configure
204 * @return 0 if OK, -ve on error
206 int pinctrl_config_pads(struct udevice *dev, u32 *pads, int pads_count);
209 * pinctrl_gpi_clear_int_cfg() - Set up the interrupts for use
211 * This enables the interrupt inputs and clears the status register bits
213 * @return 0 if OK, -ve on error
215 int pinctrl_gpi_clear_int_cfg(void);
218 * pinctrl_config_pads_for_node() - Configure pads
220 * Set up the pads using the data in a given node
222 * @dev: pinctrl device (any will do)
223 * @node: Node containing the 'pads' property with the data in it
224 * @return 0 if OK, -ve on error
226 int pinctrl_config_pads_for_node(struct udevice *dev, ofnode node);
229 * pinctrl_read_pads() - Read pad data from a node
231 * @dev: pinctrl device (any will do, it is just used to get config)
232 * @node: Node to read pad data from
233 * @prop: Property name to use (e.g. "pads")
234 * @padsp: Returns a pointer to an allocated array of pad data, in the format:
240 * The number of pad config values is set by the pinctrl controller.
241 * The caller must free this array.
242 * @pad_countp: Returns the number of pads read
243 * @ereturn 0 if OK, -ve on error
245 int pinctrl_read_pads(struct udevice *dev, ofnode node, const char *prop,
246 u32 **padsp, int *pad_countp);
249 * pinctrl_count_pads() - Count the number of pads in a pad array
251 * This used used with of-platdata where the array may be smaller than its
252 * maximum size. This function searches for the last pad in the array by finding
253 * the first 'zero' record
255 * This works out the number of records in the array. Each record has one word
256 * for the pad and num_cfgs words for the config.
258 * @dev: pinctrl device (any will do)
259 * @pads: Array of pad data
260 * @size: Size of pad data in bytes
261 * @return number of pads represented by the data
263 int pinctrl_count_pads(struct udevice *dev, u32 *pads, int size);
266 * intel_pinctrl_get_config_reg_addr() - Get address of the pin config registers
268 * @dev: Pinctrl device
269 * @offset: GPIO offset within this device
270 * @return register offset within the GPIO p2sb region
272 u32 intel_pinctrl_get_config_reg_addr(struct udevice *dev, uint offset);
275 * intel_pinctrl_get_config_reg() - Get the value of a GPIO register
277 * @dev: Pinctrl device
278 * @offset: GPIO offset within this device
279 * @return register value within the GPIO p2sb region
281 u32 intel_pinctrl_get_config_reg(struct udevice *dev, uint offset);
284 * intel_pinctrl_get_pad() - Get pad information for a pad
286 * This is used by the GPIO controller to find the pinctrl used by a pad.
289 * @devp: Returns pinctrl device containing that pad
290 * @offsetp: Returns offset of pad within that pinctrl device
292 int intel_pinctrl_get_pad(uint pad, struct udevice **devp, uint *offsetp);
295 * intel_pinctrl_get_acpi_pin() - Get the ACPI pin for a pinctrl pin
297 * Maps a pinctrl pin (in terms of its offset within the pins controlled by that
298 * pinctrl) to an ACPI GPIO pin-table entry.
300 * @dev: Pinctrl device to check
301 * @offset: Offset of pin within that device (0 = first)
302 * @return associated ACPI GPIO pin-table entry, or standard pin number if the
303 * ACPI pad base is not set
305 int intel_pinctrl_get_acpi_pin(struct udevice *dev, uint offset);