2 * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
4 * SPDX-License-Identifier: GPL-2.0+
10 /* Message Bus Ports */
11 #define MSG_PORT_MEM_ARBITER 0x00
12 #define MSG_PORT_HOST_BRIDGE 0x03
13 #define MSG_PORT_RMU 0x04
14 #define MSG_PORT_MEM_MGR 0x05
15 #define MSG_PORT_SOC_UNIT 0x31
17 /* Port 0x00: Memory Arbiter Message Port Registers */
19 /* Enhanced Configuration Space */
22 /* Port 0x03: Host Bridge Message Port Registers */
24 /* Host Miscellaneous Controls 2 */
27 #define HMISC2_SEGE 0x00000002
28 #define HMISC2_SEGF 0x00000004
29 #define HMISC2_SEGAB 0x00000010
31 /* Host Memory I/O Boundary */
34 /* Extended Configuration Space */
37 /* Port 0x04: Remote Management Unit Message Port Registers */
39 /* ACPI PBLK Base Address Register */
42 /* SPI DMA Base Address Register */
43 #define SPI_DMA_BA 0x7a
45 /* Port 0x05: Memory Manager Message Port Registers */
47 /* eSRAM Block Page Control */
48 #define ESRAM_BLK_CTRL 0x82
49 #define ESRAM_BLOCK_MODE 0x10000000
52 #define DRAM_BASE 0x00000000
53 #define DRAM_MAX_SIZE 0x80000000
56 #define ESRAM_SIZE 0x80000
58 /* Memory BAR Enable */
59 #define MEM_BAR_EN 0x00000001
62 #define IO_BAR_EN 0x80000000
64 /* 64KiB of RMU binary in flash */
65 #define RMU_BINARY_SIZE 0x10000
67 /* Legacy Bridge PCI Configuration Registers */
69 #define LB_PM1BLK 0x48
70 #define LB_GPE0BLK 0x4c
72 #define LB_PABCDRC 0x60
73 #define LB_PEFGHRC 0x64
79 #endif /* _QUARK_H_ */