2 * Copyright (C) 2013, Intel Corporation
3 * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
5 * Ported from Intel released Quark UEFI BIOS
6 * QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei
8 * SPDX-License-Identifier: Intel
14 #define MRC_VERSION 0x0111
16 /* architectural definitions */
17 #define NUM_CHANNELS 1 /* number of channels */
18 #define NUM_RANKS 2 /* number of ranks per channel */
19 #define NUM_BYTE_LANES 4 /* number of byte lanes per channel */
21 /* software limitations */
22 #define MAX_CHANNELS 1
24 #define MAX_BYTE_LANES 4
28 #define MAX_ROWS (MAX_SIDES * MAX_SOCKETS)
30 /* Specify DRAM and channel width */
33 X16, /* DRAM width & Channel Width */
34 X32 /* Channel Width */
37 /* Specify DRAM speed */
43 /* Specify DRAM type */
50 * density: 0=512Mb, 1=Gb, 2=2Gb, 3=4Gb
51 * cl: DRAM CAS Latency in clocks
52 * ras: ACT to PRE command period
53 * wtr: Delay from start of internal write transaction to internal read command
54 * rrd: ACT to ACT command period (JESD79 specific to page size 1K/2K)
55 * faw: Four activate window (JESD79 specific to page size 1K/2K)
57 * ras/wtr/rrd/faw timings are in picoseconds
59 * Refer to JEDEC spec (or DRAM datasheet) when changing these values.
71 * Delay configuration for individual signals
76 uint32_t rcvn[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
77 uint32_t rdqs[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
78 uint32_t wdqs[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
79 uint32_t wdq[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
80 uint32_t vref[NUM_CHANNELS][NUM_BYTE_LANES];
81 uint32_t wctl[NUM_CHANNELS][NUM_RANKS];
82 uint32_t wcmd[NUM_CHANNELS];
83 uint32_t scrambler_seed;
84 /* need to save for the case of frequency change */
88 /* Boot mode defined as bit mask (1<<n) */
91 BM_COLD = 1, /* full training */
92 BM_FAST = 2, /* restore timing parameters */
93 BM_S3 = 4, /* resume from S3 */
97 /* MRC execution status */
98 #define MRC_SUCCESS 0 /* initialization ok */
99 #define MRC_E_MEMTEST 1 /* memtest failed */
102 * Memory Reference Code parameters
104 * It includes 3 parts:
105 * - input parameters like boot mode and DRAM parameters
106 * - context parameters for MRC internal state
107 * - output parameters like initialization result and memory size
110 /* Input parameters */
111 uint32_t boot_mode; /* BM_COLD, BM_FAST, BM_WARM, BM_S3 */
112 /* DRAM parameters */
113 uint8_t dram_width; /* x8, x16 */
114 uint8_t ddr_speed; /* DDRFREQ_800, DDRFREQ_1066 */
115 uint8_t ddr_type; /* DDR3, DDR3L */
116 uint8_t ecc_enables; /* 0, 1 (memory size reduced to 7/8) */
117 uint8_t scrambling_enables; /* 0, 1 */
118 /* 1, 3 (1'st rank has to be populated if 2'nd rank present) */
119 uint32_t rank_enables;
120 uint32_t channel_enables; /* 1 only */
121 uint32_t channel_width; /* x16 only */
122 /* 0, 1, 2 (mode 2 forced if ecc enabled) */
123 uint32_t address_mode;
124 /* REFRESH_RATE: 1=1.95us, 2=3.9us, 3=7.8us, others=RESERVED */
125 uint8_t refresh_rate;
126 /* SR_TEMP_RANGE: 0=normal, 1=extended, others=RESERVED */
127 uint8_t sr_temp_range;
129 * RON_VALUE: 0=34ohm, 1=40ohm, others=RESERVED
130 * (select MRS1.DIC driver impedance control)
133 /* RTT_NOM_VALUE: 0=40ohm, 1=60ohm, 2=120ohm, others=RESERVED */
134 uint8_t rtt_nom_value;
135 /* RD_ODT_VALUE: 0=off, 1=60ohm, 2=120ohm, 3=180ohm, others=RESERVED */
136 uint8_t rd_odt_value;
137 struct dram_params params;
138 /* Internally used context parameters */
139 uint32_t board_id; /* board layout (use x8 or x16 memory) */
140 uint32_t hte_setup; /* when set hte reconfiguration requested */
141 uint32_t menu_after_mrc;
142 uint32_t power_down_disable;
144 uint32_t channel_size[NUM_CHANNELS];
145 uint32_t column_bits[NUM_CHANNELS];
146 uint32_t row_bits[NUM_CHANNELS];
147 uint32_t mrs1; /* register content saved during training */
149 /* Output parameters */
150 /* initialization result (non zero specifies error code) */
152 /* total memory size in bytes (excludes ECC banks) */
154 /* training results (also used on input) */
155 struct mrc_timings timings;
159 * MRC memory initialization structure
161 * post_code: a 16-bit post code of a specific initialization routine
162 * boot_path: bitwise or of BM_COLD, BM_FAST, BM_WARM and BM_S3
163 * init_fn: real memory initialization routine
168 void (*init_fn)(struct mrc_params *mrc_params);
171 /* MRC platform data flags */
172 #define MRC_FLAG_ECC_EN 0x00000001
173 #define MRC_FLAG_SCRAMBLE_EN 0x00000002
174 #define MRC_FLAG_MEMTEST_EN 0x00000004
175 /* 0b DDR "fly-by" topology else 1b DDR "tree" topology */
176 #define MRC_FLAG_TOP_TREE_EN 0x00000008
177 /* If set ODR signal is asserted to DRAM devices on writes */
178 #define MRC_FLAG_WR_ODT_EN 0x00000010
181 * mrc_init - Memory Reference Code initialization entry routine
183 * @mrc_params: parameters for MRC
185 void mrc_init(struct mrc_params *mrc_params);