2 * Copyright (c) 2014 Google, Inc
4 * From Coreboot file of the same name
6 * Copyright (C) 2007-2008 coresystems GmbH
7 * Copyright (C) 2011 Google Inc.
9 * SPDX-License-Identifier: GPL-2.0
12 #ifndef _ACH_ASM_SANDYBRIDGE_H
13 #define _ACH_ASM_SANDYBRIDGE_H
16 #define SANDYBRIDGE_MOBILE 0
17 #define SANDYBRIDGE_DESKTOP 1
18 #define SANDYBRIDGE_SERVER 2
20 /* Device ID for SandyBridge and IvyBridge */
21 #define BASE_REV_SNB 0x00
22 #define BASE_REV_IVB 0x50
23 #define BASE_REV_MASK 0x50
25 /* SandyBridge CPU stepping */
26 #define SNB_STEP_D0 (BASE_REV_SNB + 5) /* Also J0 */
27 #define SNB_STEP_D1 (BASE_REV_SNB + 6)
28 #define SNB_STEP_D2 (BASE_REV_SNB + 7) /* Also J1/Q0 */
30 /* IvyBridge CPU stepping */
31 #define IVB_STEP_A0 (BASE_REV_IVB + 0)
32 #define IVB_STEP_B0 (BASE_REV_IVB + 2)
33 #define IVB_STEP_C0 (BASE_REV_IVB + 4)
34 #define IVB_STEP_K0 (BASE_REV_IVB + 5)
35 #define IVB_STEP_D0 (BASE_REV_IVB + 6)
37 /* Intel Enhanced Debug region must be 4MB */
38 #define IED_SIZE 0x400000
40 /* Northbridge BARs */
41 #define DEFAULT_MCHBAR 0xfed10000 /* 16 KB */
42 #define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */
43 #define DEFAULT_EPBAR 0xfed19000 /* 4 KB */
44 #define DEFAULT_RCBABASE 0xfed1c000
45 /* 4 KB per PCIe device */
46 #define DEFAULT_PCIEXBAR CONFIG_PCIE_ECAM_BASE
48 /* Device 0:0.0 PCI configuration space (Host Bridge) */
55 #define GGC 0x50 /* GMCH Graphics Control */
57 #define DEVEN 0x54 /* Device Enable */
58 #define DEVEN_PEG60 (1 << 13)
59 #define DEVEN_IGD (1 << 4)
60 #define DEVEN_PEG10 (1 << 3)
61 #define DEVEN_PEG11 (1 << 2)
62 #define DEVEN_PEG12 (1 << 1)
63 #define DEVEN_HOST (1 << 0)
73 #define LAC 0x87 /* Legacy Access Control */
74 #define SMRAM 0x88 /* System Management RAM Control */
75 #define D_OPEN (1 << 6)
76 #define D_CLS (1 << 5)
77 #define D_LCK (1 << 4)
78 #define G_SMRAME (1 << 3)
79 #define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0))
82 #define TOUUD 0xa8 /* Top of Upper Usable DRAM */
83 #define TSEG 0xb8 /* TSEG base */
84 #define TOLUD 0xbc /* Top of Low Used Memory */
86 #define SKPAD 0xdc /* Scratchpad Data */
88 /* Device 0:1.0 PCI configuration space (PCI Express) */
89 #define BCTRL1 0x3e /* 16bit */
91 /* Device 0:2.0 PCI configuration space (Graphics Device) */
93 #define MSAC 0x62 /* Multi Size Aperture Control */
94 #define SWSCI 0xe8 /* SWSCI enable */
95 #define ASLS 0xfc /* OpRegion Base */
100 #define MCHBAR_REG(reg) (DEFAULT_MCHBAR + (reg))
102 #define SSKPD 0x5d14 /* 16bit (scratchpad) */
103 #define BIOS_RESET_CPL 0x5da8 /* 8bit */
109 #define DMIBAR_REG(x) (DEFAULT_DMIBAR + x)
111 int bridge_silicon_revision(void);
113 void northbridge_enable(pci_dev_t dev);
114 void northbridge_init(pci_dev_t dev);
116 void report_platform_info(void);
118 void sandybridge_early_init(int chipset_type);