2 * Copyright (c) 2014 Google, Inc
4 * From Coreboot src/southbridge/intel/bd82x6x/pch.h
6 * Copyright (C) 2008-2009 coresystems GmbH
7 * Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
9 * SPDX-License-Identifier: GPL-2.0
12 #ifndef _ASM_ARCH_PCH_H
13 #define _ASM_ARCH_PCH_H
18 #define PCH_TYPE_CPT 0x1c /* CougarPoint */
19 #define PCH_TYPE_PPT 0x1e /* IvyBridge */
21 /* PCH stepping values for LPC device */
28 #define DEFAULT_GPIOBASE 0x0480
29 #define DEFAULT_PMBASE 0x0500
31 #define SMBUS_IO_BASE 0x0400
33 int pch_silicon_revision(void);
34 int pch_silicon_type(void);
35 int pch_silicon_supported(int type, int rev);
36 void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue);
38 #define MAINBOARD_POWER_OFF 0
39 #define MAINBOARD_POWER_ON 1
40 #define MAINBOARD_POWER_KEEP 2
42 /* PCI Configuration Space (D30:F0): PCI2PCI */
52 #define PCH_EHCI1_DEV PCI_BDF(0, 0x1d, 0)
53 #define PCH_EHCI2_DEV PCI_BDF(0, 0x1a, 0)
54 #define PCH_XHCI_DEV PCI_BDF(0, 0x14, 0)
55 #define PCH_ME_DEV PCI_BDF(0, 0x16, 0)
56 #define PCH_PCIE_DEV_SLOT 28
58 #define PCH_DEV PCI_BDF(0, 0, 0)
59 #define PCH_VIDEO_DEV PCI_BDF(0, 2, 0)
61 /* PCI Configuration Space (D31:F0): LPC */
62 #define PCH_LPC_DEV PCI_BDF(0, 0x1f, 0)
63 #define SERIRQ_CNTL 0x64
65 #define GEN_PMCON_1 0xa0
66 #define GEN_PMCON_2 0xa2
67 #define GEN_PMCON_3 0xa4
69 #define ETR3_CWORWRE (1 << 18)
70 #define ETR3_CF9GR (1 << 20)
72 /* GEN_PMCON_3 bits */
73 #define RTC_BATTERY_DEAD (1 << 2)
74 #define RTC_POWER_FAILED (1 << 1)
75 #define SLEEP_AFTER_POWER_FAIL (1 << 0)
78 #define ACPI_CNTL 0x44
79 #define BIOS_CNTL 0xDC
80 #define GPIO_BASE 0x48 /* LPC GPIO Base Address Register */
81 #define GPIO_CNTL 0x4C /* LPC GPIO Control Register */
82 #define GPIO_ROUT 0xb8
84 #define PIRQA_ROUT 0x60
85 #define PIRQB_ROUT 0x61
86 #define PIRQC_ROUT 0x62
87 #define PIRQD_ROUT 0x63
88 #define PIRQE_ROUT 0x68
89 #define PIRQF_ROUT 0x69
90 #define PIRQG_ROUT 0x6A
91 #define PIRQH_ROUT 0x6B
93 #define GEN_PMCON_1 0xa0
94 #define GEN_PMCON_2 0xa2
95 #define GEN_PMCON_3 0xa4
97 #define ETR3_CWORWRE (1 << 18)
98 #define ETR3_CF9GR (1 << 20)
101 #define ACPI_CNTL 0x44
102 #define BIOS_CNTL 0xDC
103 #define GPIO_BASE 0x48 /* LPC GPIO Base Address Register */
104 #define GPIO_CNTL 0x4C /* LPC GPIO Control Register */
105 #define GPIO_ROUT 0xb8
107 #define LPC_IO_DEC 0x80 /* IO Decode Ranges Register */
108 #define LPC_EN 0x82 /* LPC IF Enables Register */
109 #define CNF2_LPC_EN (1 << 13) /* 0x4e/0x4f */
110 #define CNF1_LPC_EN (1 << 12) /* 0x2e/0x2f */
111 #define MC_LPC_EN (1 << 11) /* 0x62/0x66 */
112 #define KBC_LPC_EN (1 << 10) /* 0x60/0x64 */
113 #define GAMEH_LPC_EN (1 << 9) /* 0x208/0x20f */
114 #define GAMEL_LPC_EN (1 << 8) /* 0x200/0x207 */
115 #define FDD_LPC_EN (1 << 3) /* LPC_IO_DEC[12] */
116 #define LPT_LPC_EN (1 << 2) /* LPC_IO_DEC[9:8] */
117 #define COMB_LPC_EN (1 << 1) /* LPC_IO_DEC[6:4] */
118 #define COMA_LPC_EN (1 << 0) /* LPC_IO_DEC[3:2] */
119 #define LPC_GEN1_DEC 0x84 /* LPC IF Generic Decode Range 1 */
120 #define LPC_GEN2_DEC 0x88 /* LPC IF Generic Decode Range 2 */
121 #define LPC_GEN3_DEC 0x8c /* LPC IF Generic Decode Range 3 */
122 #define LPC_GEN4_DEC 0x90 /* LPC IF Generic Decode Range 4 */
123 #define LPC_GENX_DEC(x) (0x84 + 4 * (x))
125 /* PCI Configuration Space (D31:F3): SMBus */
126 #define PCH_SMBUS_DEV PCI_BDF(0, 0x1f, 3)
127 #define SMB_BASE 0x20
129 #define SMB_RCV_SLVA 0x09
132 #define I2C_EN (1 << 2)
133 #define SMB_SMI_EN (1 << 1)
134 #define HST_EN (1 << 0)
136 /* SMBus I/O bits. */
137 #define SMBHSTSTAT 0x0
138 #define SMBHSTCTL 0x2
139 #define SMBHSTCMD 0x3
140 #define SMBXMITADD 0x4
141 #define SMBHSTDAT0 0x5
142 #define SMBHSTDAT1 0x6
143 #define SMBBLKDAT 0x7
144 #define SMBTRNSADD 0x9
145 #define SMBSLVDATA 0xa
146 #define SMLINK_PIN_CTL 0xe
147 #define SMBUS_PIN_CTL 0xf
149 #define SMBUS_TIMEOUT (10 * 1000 * 100)
152 /* Root Complex Register Block */
153 #define DEFAULT_RCBA 0xfed1c000
154 #define RCB_REG(reg) (DEFAULT_RCBA + (reg))
156 #define PCH_RCBA_BASE 0xf0
158 #define VCH 0x0000 /* 32bit */
159 #define VCAP1 0x0004 /* 32bit */
160 #define VCAP2 0x0008 /* 32bit */
161 #define PVC 0x000c /* 16bit */
162 #define PVS 0x000e /* 16bit */
164 #define V0CAP 0x0010 /* 32bit */
165 #define V0CTL 0x0014 /* 32bit */
166 #define V0STS 0x001a /* 16bit */
168 #define V1CAP 0x001c /* 32bit */
169 #define V1CTL 0x0020 /* 32bit */
170 #define V1STS 0x0026 /* 16bit */
172 #define RCTCL 0x0100 /* 32bit */
173 #define ESD 0x0104 /* 32bit */
174 #define ULD 0x0110 /* 32bit */
175 #define ULBA 0x0118 /* 64bit */
177 #define RP1D 0x0120 /* 32bit */
178 #define RP1BA 0x0128 /* 64bit */
179 #define RP2D 0x0130 /* 32bit */
180 #define RP2BA 0x0138 /* 64bit */
181 #define RP3D 0x0140 /* 32bit */
182 #define RP3BA 0x0148 /* 64bit */
183 #define RP4D 0x0150 /* 32bit */
184 #define RP4BA 0x0158 /* 64bit */
185 #define HDD 0x0160 /* 32bit */
186 #define HDBA 0x0168 /* 64bit */
187 #define RP5D 0x0170 /* 32bit */
188 #define RP5BA 0x0178 /* 64bit */
189 #define RP6D 0x0180 /* 32bit */
190 #define RP6BA 0x0188 /* 64bit */
192 #define RPC 0x0400 /* 32bit */
193 #define RPFN 0x0404 /* 32bit */
195 #define TRSR 0x1e00 /* 8bit */
196 #define TRCR 0x1e10 /* 64bit */
197 #define TWDR 0x1e18 /* 64bit */
199 #define IOTR0 0x1e80 /* 64bit */
200 #define IOTR1 0x1e88 /* 64bit */
201 #define IOTR2 0x1e90 /* 64bit */
202 #define IOTR3 0x1e98 /* 64bit */
204 #define TCTL 0x3000 /* 8bit */
212 #define DIR_IDR 12 /* Interrupt D Pin Offset */
213 #define DIR_ICR 8 /* Interrupt C Pin Offset */
214 #define DIR_IBR 4 /* Interrupt B Pin Offset */
215 #define DIR_IAR 0 /* Interrupt A Pin Offset */
226 /* IO Buffer Programming */
227 #define IOBPIRI 0x2330
230 #define IOBPS_RW_BX ((1 << 9)|(1 << 10))
231 #define IOBPS_WRITE_AX ((1 << 9)|(1 << 10))
232 #define IOBPS_READ_AX ((1 << 8)|(1 << 9)|(1 << 10))
234 #define D31IP 0x3100 /* 32bit */
235 #define D31IP_TTIP 24 /* Thermal Throttle Pin */
236 #define D31IP_SIP2 20 /* SATA Pin 2 */
237 #define D31IP_SMIP 12 /* SMBUS Pin */
238 #define D31IP_SIP 8 /* SATA Pin */
239 #define D30IP 0x3104 /* 32bit */
240 #define D30IP_PIP 0 /* PCI Bridge Pin */
241 #define D29IP 0x3108 /* 32bit */
242 #define D29IP_E1P 0 /* EHCI #1 Pin */
243 #define D28IP 0x310c /* 32bit */
244 #define D28IP_P8IP 28 /* PCI Express Port 8 */
245 #define D28IP_P7IP 24 /* PCI Express Port 7 */
246 #define D28IP_P6IP 20 /* PCI Express Port 6 */
247 #define D28IP_P5IP 16 /* PCI Express Port 5 */
248 #define D28IP_P4IP 12 /* PCI Express Port 4 */
249 #define D28IP_P3IP 8 /* PCI Express Port 3 */
250 #define D28IP_P2IP 4 /* PCI Express Port 2 */
251 #define D28IP_P1IP 0 /* PCI Express Port 1 */
252 #define D27IP 0x3110 /* 32bit */
253 #define D27IP_ZIP 0 /* HD Audio Pin */
254 #define D26IP 0x3114 /* 32bit */
255 #define D26IP_E2P 0 /* EHCI #2 Pin */
256 #define D25IP 0x3118 /* 32bit */
257 #define D25IP_LIP 0 /* GbE LAN Pin */
258 #define D22IP 0x3124 /* 32bit */
259 #define D22IP_KTIP 12 /* KT Pin */
260 #define D22IP_IDERIP 8 /* IDE-R Pin */
261 #define D22IP_MEI2IP 4 /* MEI #2 Pin */
262 #define D22IP_MEI1IP 0 /* MEI #1 Pin */
263 #define D20IP 0x3128 /* 32bit */
264 #define D20IP_XHCIIP 0
265 #define D31IR 0x3140 /* 16bit */
266 #define D30IR 0x3142 /* 16bit */
267 #define D29IR 0x3144 /* 16bit */
268 #define D28IR 0x3146 /* 16bit */
269 #define D27IR 0x3148 /* 16bit */
270 #define D26IR 0x314c /* 16bit */
271 #define D25IR 0x3150 /* 16bit */
272 #define D22IR 0x315c /* 16bit */
273 #define D20IR 0x3160 /* 16bit */
274 #define OIC 0x31fe /* 16bit */
276 #define SPI_FREQ_SWSEQ 0x3893
277 #define SPI_DESC_COMP0 0x38b0
278 #define SPI_FREQ_WR_ERA 0x38b4
279 #define SOFT_RESET_CTRL 0x38f4
280 #define SOFT_RESET_DATA 0x38f8
282 #define DIR_ROUTE(a, b, c, d) \
283 (((d) << DIR_IDR) | ((c) << DIR_ICR) | \
284 ((b) << DIR_IBR) | ((a) << DIR_IAR))
286 #define RC 0x3400 /* 32bit */
287 #define HPTC 0x3404 /* 32bit */
288 #define GCS 0x3410 /* 32bit */
289 #define BUC 0x3414 /* 32bit */
290 #define PCH_DISABLE_GBE (1 << 5)
291 #define FD 0x3418 /* 32bit */
292 #define DISPBDF 0x3424 /* 16bit */
293 #define FD2 0x3428 /* 32bit */
294 #define CG 0x341c /* 32bit */
296 /* Function Disable 1 RCBA 0x3418 */
297 #define PCH_DISABLE_ALWAYS ((1 << 0)|(1 << 26))
298 #define PCH_DISABLE_P2P (1 << 1)
299 #define PCH_DISABLE_SATA1 (1 << 2)
300 #define PCH_DISABLE_SMBUS (1 << 3)
301 #define PCH_DISABLE_HD_AUDIO (1 << 4)
302 #define PCH_DISABLE_EHCI2 (1 << 13)
303 #define PCH_DISABLE_LPC (1 << 14)
304 #define PCH_DISABLE_EHCI1 (1 << 15)
305 #define PCH_DISABLE_PCIE(x) (1 << (16 + x))
306 #define PCH_DISABLE_THERMAL (1 << 24)
307 #define PCH_DISABLE_SATA2 (1 << 25)
308 #define PCH_DISABLE_XHCI (1 << 27)
310 /* Function Disable 2 RCBA 0x3428 */
311 #define PCH_DISABLE_KT (1 << 4)
312 #define PCH_DISABLE_IDER (1 << 3)
313 #define PCH_DISABLE_MEI2 (1 << 2)
314 #define PCH_DISABLE_MEI1 (1 << 1)
315 #define PCH_ENABLE_DBDF (1 << 0)
318 #define GPIO_USE_SEL 0x00
319 #define GP_IO_SEL 0x04
321 #define GPO_BLINK 0x18
323 #define GPIO_USE_SEL2 0x30
324 #define GP_IO_SEL2 0x34
326 #define GPIO_USE_SEL3 0x40
327 #define GP_IO_SEL3 0x44
329 #define GP_RST_SEL1 0x60
330 #define GP_RST_SEL2 0x64
331 #define GP_RST_SEL3 0x68
335 #define WAK_STS (1 << 15)
336 #define PCIEXPWAK_STS (1 << 14)
337 #define PRBTNOR_STS (1 << 11)
338 #define RTC_STS (1 << 10)
339 #define PWRBTN_STS (1 << 8)
340 #define GBL_STS (1 << 5)
341 #define BM_STS (1 << 4)
342 #define TMROF_STS (1 << 0)
344 #define PCIEXPWAK_DIS (1 << 14)
345 #define RTC_EN (1 << 10)
346 #define PWRBTN_EN (1 << 8)
347 #define GBL_EN (1 << 5)
348 #define TMROF_EN (1 << 0)
350 #define SLP_EN (1 << 13)
351 #define SLP_TYP (7 << 10)
357 #define GBL_RLS (1 << 2)
358 #define BM_RLD (1 << 1)
359 #define SCI_EN (1 << 0)
361 #define PROC_CNT 0x10
365 #define PM2_CNT 0x50 /* mobile only */
366 #define GPE0_STS 0x20
367 #define PME_B0_STS (1 << 13)
368 #define PME_STS (1 << 11)
369 #define BATLOW_STS (1 << 10)
370 #define PCI_EXP_STS (1 << 9)
371 #define RI_STS (1 << 8)
372 #define SMB_WAK_STS (1 << 7)
373 #define TCOSCI_STS (1 << 6)
374 #define SWGPE_STS (1 << 2)
375 #define HOT_PLUG_STS (1 << 1)
377 #define PME_B0_EN (1 << 13)
378 #define PME_EN (1 << 11)
379 #define TCOSCI_EN (1 << 6)
381 #define INTEL_USB2_EN (1 << 18) /* Intel-Specific USB2 SMI logic */
382 #define LEGACY_USB2_EN (1 << 17) /* Legacy USB2 SMI logic */
383 #define PERIODIC_EN (1 << 14) /* SMI on PERIODIC_STS in SMI_STS */
384 #define TCO_EN (1 << 13) /* Enable TCO Logic (BIOSWE et al) */
385 #define MCSMI_EN (1 << 11) /* Trap microcontroller range access */
386 #define BIOS_RLS (1 << 7) /* asserts SCI on bit set */
387 #define SWSMI_TMR_EN (1 << 6) /* start software smi timer on bit set */
388 #define APMC_EN (1 << 5) /* Writes to APM_CNT cause SMI# */
389 #define SLP_SMI_EN (1 << 4) /* Write SLP_EN in PM1_CNT asserts SMI# */
390 #define LEGACY_USB_EN (1 << 3) /* Legacy USB circuit SMI logic */
391 #define BIOS_EN (1 << 2) /* Assert SMI# on setting GBL_RLS bit */
392 #define EOS (1 << 1) /* End of SMI (deassert SMI#) */
393 #define GBL_SMI_EN (1 << 0) /* SMI# generation at all? */
395 #define ALT_GP_SMI_EN 0x38
396 #define ALT_GP_SMI_STS 0x3a
397 #define GPE_CNTL 0x42
398 #define DEVACT_STS 0x44
401 #define TCO1_STS 0x64
402 #define DMISCI_STS (1 << 9)
403 #define TCO2_STS 0x66
405 int lpc_init(struct pci_controller *hose, pci_dev_t dev);
406 void lpc_enable(pci_dev_t dev);
409 * lpc_early_init() - set up LPC serial ports and other early things
411 * @blob: Device tree blob
412 * @node: Offset of LPC node
413 * @dev: PCH PCI device containing the LPC
414 * @return 0 if OK, -ve on error
416 int lpc_early_init(const void *blob, int node, pci_dev_t dev);