2 * Copyright (c) 2014 Google, Inc
4 * From Coreboot src/southbridge/intel/bd82x6x/pch.h
6 * Copyright (C) 2008-2009 coresystems GmbH
7 * Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
9 * SPDX-License-Identifier: GPL-2.0
12 #ifndef _ASM_ARCH_PCH_H
13 #define _ASM_ARCH_PCH_H
17 #define DEFAULT_GPIOBASE 0x0480
18 #define DEFAULT_PMBASE 0x0500
20 #define SMBUS_IO_BASE 0x0400
22 /* PCI Configuration Space (D30:F0): PCI2PCI */
32 #define PCH_EHCI1_DEV PCI_BDF(0, 0x1d, 0)
33 #define PCH_EHCI2_DEV PCI_BDF(0, 0x1a, 0)
34 #define PCH_XHCI_DEV PCI_BDF(0, 0x14, 0)
35 #define PCH_ME_DEV PCI_BDF(0, 0x16, 0)
36 #define PCH_PCIE_DEV_SLOT 28
38 #define PCH_DEV PCI_BDF(0, 0, 0)
39 #define PCH_VIDEO_DEV PCI_BDF(0, 2, 0)
41 /* PCI Configuration Space (D31:F0): LPC */
42 #define PCH_LPC_DEV PCI_BDF(0, 0x1f, 0)
44 #define GEN_PMCON_1 0xa0
45 #define GEN_PMCON_2 0xa2
46 #define GEN_PMCON_3 0xa4
48 #define ETR3_CWORWRE (1 << 18)
49 #define ETR3_CF9GR (1 << 20)
52 #define ACPI_CNTL 0x44
53 #define BIOS_CNTL 0xDC
54 #define GPIO_BASE 0x48 /* LPC GPIO Base Address Register */
55 #define GPIO_CNTL 0x4C /* LPC GPIO Control Register */
56 #define GPIO_ROUT 0xb8
58 #define LPC_IO_DEC 0x80 /* IO Decode Ranges Register */
59 #define LPC_EN 0x82 /* LPC IF Enables Register */
60 #define CNF2_LPC_EN (1 << 13) /* 0x4e/0x4f */
61 #define CNF1_LPC_EN (1 << 12) /* 0x2e/0x2f */
62 #define MC_LPC_EN (1 << 11) /* 0x62/0x66 */
63 #define KBC_LPC_EN (1 << 10) /* 0x60/0x64 */
64 #define GAMEH_LPC_EN (1 << 9) /* 0x208/0x20f */
65 #define GAMEL_LPC_EN (1 << 8) /* 0x200/0x207 */
66 #define FDD_LPC_EN (1 << 3) /* LPC_IO_DEC[12] */
67 #define LPT_LPC_EN (1 << 2) /* LPC_IO_DEC[9:8] */
68 #define COMB_LPC_EN (1 << 1) /* LPC_IO_DEC[6:4] */
69 #define COMA_LPC_EN (1 << 0) /* LPC_IO_DEC[3:2] */
70 #define LPC_GEN1_DEC 0x84 /* LPC IF Generic Decode Range 1 */
71 #define LPC_GEN2_DEC 0x88 /* LPC IF Generic Decode Range 2 */
72 #define LPC_GEN3_DEC 0x8c /* LPC IF Generic Decode Range 3 */
73 #define LPC_GEN4_DEC 0x90 /* LPC IF Generic Decode Range 4 */
74 #define LPC_GENX_DEC(x) (0x84 + 4 * (x))
76 /* PCI Configuration Space (D31:F3): SMBus */
77 #define PCH_SMBUS_DEV PCI_BDF(0, 0x1f, 3)
80 #define SMB_RCV_SLVA 0x09
83 #define I2C_EN (1 << 2)
84 #define SMB_SMI_EN (1 << 1)
85 #define HST_EN (1 << 0)
88 #define SMBHSTSTAT 0x0
91 #define SMBXMITADD 0x4
92 #define SMBHSTDAT0 0x5
93 #define SMBHSTDAT1 0x6
95 #define SMBTRNSADD 0x9
96 #define SMBSLVDATA 0xa
97 #define SMLINK_PIN_CTL 0xe
98 #define SMBUS_PIN_CTL 0xf
100 #define SMBUS_TIMEOUT (10 * 1000 * 100)
103 /* Root Complex Register Block */
104 #define DEFAULT_RCBA 0xfed1c000
105 #define RCB_REG(reg) (DEFAULT_RCBA + (reg))
107 #define PCH_RCBA_BASE 0xf0
109 #define VCH 0x0000 /* 32bit */
110 #define VCAP1 0x0004 /* 32bit */
111 #define VCAP2 0x0008 /* 32bit */
112 #define PVC 0x000c /* 16bit */
113 #define PVS 0x000e /* 16bit */
115 #define V0CAP 0x0010 /* 32bit */
116 #define V0CTL 0x0014 /* 32bit */
117 #define V0STS 0x001a /* 16bit */
119 #define V1CAP 0x001c /* 32bit */
120 #define V1CTL 0x0020 /* 32bit */
121 #define V1STS 0x0026 /* 16bit */
123 #define RCTCL 0x0100 /* 32bit */
124 #define ESD 0x0104 /* 32bit */
125 #define ULD 0x0110 /* 32bit */
126 #define ULBA 0x0118 /* 64bit */
128 #define RP1D 0x0120 /* 32bit */
129 #define RP1BA 0x0128 /* 64bit */
130 #define RP2D 0x0130 /* 32bit */
131 #define RP2BA 0x0138 /* 64bit */
132 #define RP3D 0x0140 /* 32bit */
133 #define RP3BA 0x0148 /* 64bit */
134 #define RP4D 0x0150 /* 32bit */
135 #define RP4BA 0x0158 /* 64bit */
136 #define HDD 0x0160 /* 32bit */
137 #define HDBA 0x0168 /* 64bit */
138 #define RP5D 0x0170 /* 32bit */
139 #define RP5BA 0x0178 /* 64bit */
140 #define RP6D 0x0180 /* 32bit */
141 #define RP6BA 0x0188 /* 64bit */
143 #define RPC 0x0400 /* 32bit */
144 #define RPFN 0x0404 /* 32bit */
146 #define TRSR 0x1e00 /* 8bit */
147 #define TRCR 0x1e10 /* 64bit */
148 #define TWDR 0x1e18 /* 64bit */
150 #define IOTR0 0x1e80 /* 64bit */
151 #define IOTR1 0x1e88 /* 64bit */
152 #define IOTR2 0x1e90 /* 64bit */
153 #define IOTR3 0x1e98 /* 64bit */
155 #define TCTL 0x3000 /* 8bit */
163 #define DIR_IDR 12 /* Interrupt D Pin Offset */
164 #define DIR_ICR 8 /* Interrupt C Pin Offset */
165 #define DIR_IBR 4 /* Interrupt B Pin Offset */
166 #define DIR_IAR 0 /* Interrupt A Pin Offset */
177 /* IO Buffer Programming */
178 #define IOBPIRI 0x2330
181 #define IOBPS_RW_BX ((1 << 9)|(1 << 10))
182 #define IOBPS_WRITE_AX ((1 << 9)|(1 << 10))
183 #define IOBPS_READ_AX ((1 << 8)|(1 << 9)|(1 << 10))
185 #define D31IP 0x3100 /* 32bit */
186 #define D31IP_TTIP 24 /* Thermal Throttle Pin */
187 #define D31IP_SIP2 20 /* SATA Pin 2 */
188 #define D31IP_SMIP 12 /* SMBUS Pin */
189 #define D31IP_SIP 8 /* SATA Pin */
190 #define D30IP 0x3104 /* 32bit */
191 #define D30IP_PIP 0 /* PCI Bridge Pin */
192 #define D29IP 0x3108 /* 32bit */
193 #define D29IP_E1P 0 /* EHCI #1 Pin */
194 #define D28IP 0x310c /* 32bit */
195 #define D28IP_P8IP 28 /* PCI Express Port 8 */
196 #define D28IP_P7IP 24 /* PCI Express Port 7 */
197 #define D28IP_P6IP 20 /* PCI Express Port 6 */
198 #define D28IP_P5IP 16 /* PCI Express Port 5 */
199 #define D28IP_P4IP 12 /* PCI Express Port 4 */
200 #define D28IP_P3IP 8 /* PCI Express Port 3 */
201 #define D28IP_P2IP 4 /* PCI Express Port 2 */
202 #define D28IP_P1IP 0 /* PCI Express Port 1 */
203 #define D27IP 0x3110 /* 32bit */
204 #define D27IP_ZIP 0 /* HD Audio Pin */
205 #define D26IP 0x3114 /* 32bit */
206 #define D26IP_E2P 0 /* EHCI #2 Pin */
207 #define D25IP 0x3118 /* 32bit */
208 #define D25IP_LIP 0 /* GbE LAN Pin */
209 #define D22IP 0x3124 /* 32bit */
210 #define D22IP_KTIP 12 /* KT Pin */
211 #define D22IP_IDERIP 8 /* IDE-R Pin */
212 #define D22IP_MEI2IP 4 /* MEI #2 Pin */
213 #define D22IP_MEI1IP 0 /* MEI #1 Pin */
214 #define D20IP 0x3128 /* 32bit */
215 #define D20IP_XHCIIP 0
216 #define D31IR 0x3140 /* 16bit */
217 #define D30IR 0x3142 /* 16bit */
218 #define D29IR 0x3144 /* 16bit */
219 #define D28IR 0x3146 /* 16bit */
220 #define D27IR 0x3148 /* 16bit */
221 #define D26IR 0x314c /* 16bit */
222 #define D25IR 0x3150 /* 16bit */
223 #define D22IR 0x315c /* 16bit */
224 #define D20IR 0x3160 /* 16bit */
225 #define OIC 0x31fe /* 16bit */
227 #define SPI_FREQ_SWSEQ 0x3893
228 #define SPI_DESC_COMP0 0x38b0
229 #define SPI_FREQ_WR_ERA 0x38b4
230 #define SOFT_RESET_CTRL 0x38f4
231 #define SOFT_RESET_DATA 0x38f8
233 #define DIR_ROUTE(a, b, c, d) \
234 (((d) << DIR_IDR) | ((c) << DIR_ICR) | \
235 ((b) << DIR_IBR) | ((a) << DIR_IAR))
237 #define RC 0x3400 /* 32bit */
238 #define HPTC 0x3404 /* 32bit */
239 #define GCS 0x3410 /* 32bit */
240 #define BUC 0x3414 /* 32bit */
241 #define PCH_DISABLE_GBE (1 << 5)
242 #define FD 0x3418 /* 32bit */
243 #define DISPBDF 0x3424 /* 16bit */
244 #define FD2 0x3428 /* 32bit */
245 #define CG 0x341c /* 32bit */
247 /* Function Disable 1 RCBA 0x3418 */
248 #define PCH_DISABLE_ALWAYS ((1 << 0)|(1 << 26))
249 #define PCH_DISABLE_P2P (1 << 1)
250 #define PCH_DISABLE_SATA1 (1 << 2)
251 #define PCH_DISABLE_SMBUS (1 << 3)
252 #define PCH_DISABLE_HD_AUDIO (1 << 4)
253 #define PCH_DISABLE_EHCI2 (1 << 13)
254 #define PCH_DISABLE_LPC (1 << 14)
255 #define PCH_DISABLE_EHCI1 (1 << 15)
256 #define PCH_DISABLE_PCIE(x) (1 << (16 + x))
257 #define PCH_DISABLE_THERMAL (1 << 24)
258 #define PCH_DISABLE_SATA2 (1 << 25)
259 #define PCH_DISABLE_XHCI (1 << 27)
261 /* Function Disable 2 RCBA 0x3428 */
262 #define PCH_DISABLE_KT (1 << 4)
263 #define PCH_DISABLE_IDER (1 << 3)
264 #define PCH_DISABLE_MEI2 (1 << 2)
265 #define PCH_DISABLE_MEI1 (1 << 1)
266 #define PCH_ENABLE_DBDF (1 << 0)
269 #define GPIO_USE_SEL 0x00
270 #define GP_IO_SEL 0x04
272 #define GPO_BLINK 0x18
274 #define GPIO_USE_SEL2 0x30
275 #define GP_IO_SEL2 0x34
277 #define GPIO_USE_SEL3 0x40
278 #define GP_IO_SEL3 0x44
280 #define GP_RST_SEL1 0x60
281 #define GP_RST_SEL2 0x64
282 #define GP_RST_SEL3 0x68
286 #define WAK_STS (1 << 15)
287 #define PCIEXPWAK_STS (1 << 14)
288 #define PRBTNOR_STS (1 << 11)
289 #define RTC_STS (1 << 10)
290 #define PWRBTN_STS (1 << 8)
291 #define GBL_STS (1 << 5)
292 #define BM_STS (1 << 4)
293 #define TMROF_STS (1 << 0)
295 #define PCIEXPWAK_DIS (1 << 14)
296 #define RTC_EN (1 << 10)
297 #define PWRBTN_EN (1 << 8)
298 #define GBL_EN (1 << 5)
299 #define TMROF_EN (1 << 0)
301 #define SLP_EN (1 << 13)
302 #define SLP_TYP (7 << 10)
308 #define GBL_RLS (1 << 2)
309 #define BM_RLD (1 << 1)
310 #define SCI_EN (1 << 0)
312 #define PROC_CNT 0x10
316 #define PM2_CNT 0x50 /* mobile only */
317 #define GPE0_STS 0x20
318 #define PME_B0_STS (1 << 13)
319 #define PME_STS (1 << 11)
320 #define BATLOW_STS (1 << 10)
321 #define PCI_EXP_STS (1 << 9)
322 #define RI_STS (1 << 8)
323 #define SMB_WAK_STS (1 << 7)
324 #define TCOSCI_STS (1 << 6)
325 #define SWGPE_STS (1 << 2)
326 #define HOT_PLUG_STS (1 << 1)
328 #define PME_B0_EN (1 << 13)
329 #define PME_EN (1 << 11)
330 #define TCOSCI_EN (1 << 6)
332 #define INTEL_USB2_EN (1 << 18) /* Intel-Specific USB2 SMI logic */
333 #define LEGACY_USB2_EN (1 << 17) /* Legacy USB2 SMI logic */
334 #define PERIODIC_EN (1 << 14) /* SMI on PERIODIC_STS in SMI_STS */
335 #define TCO_EN (1 << 13) /* Enable TCO Logic (BIOSWE et al) */
336 #define MCSMI_EN (1 << 11) /* Trap microcontroller range access */
337 #define BIOS_RLS (1 << 7) /* asserts SCI on bit set */
338 #define SWSMI_TMR_EN (1 << 6) /* start software smi timer on bit set */
339 #define APMC_EN (1 << 5) /* Writes to APM_CNT cause SMI# */
340 #define SLP_SMI_EN (1 << 4) /* Write SLP_EN in PM1_CNT asserts SMI# */
341 #define LEGACY_USB_EN (1 << 3) /* Legacy USB circuit SMI logic */
342 #define BIOS_EN (1 << 2) /* Assert SMI# on setting GBL_RLS bit */
343 #define EOS (1 << 1) /* End of SMI (deassert SMI#) */
344 #define GBL_SMI_EN (1 << 0) /* SMI# generation at all? */
346 #define ALT_GP_SMI_EN 0x38
347 #define ALT_GP_SMI_STS 0x3a
348 #define GPE_CNTL 0x42
349 #define DEVACT_STS 0x44
352 #define TCO1_STS 0x64
353 #define DMISCI_STS (1 << 9)
354 #define TCO2_STS 0x66
356 int lpc_init(struct pci_controller *hose, pci_dev_t dev);
357 void lpc_enable(pci_dev_t dev);
360 * lpc_early_init() - set up LPC serial ports and other early things
362 * @blob: Device tree blob
363 * @node: Offset of LPC node
364 * @dev: PCH PCI device containing the LPC
365 * @return 0 if OK, -ve on error
367 int lpc_early_init(const void *blob, int node, pci_dev_t dev);