2 * Copyright (C) 2014 Google Inc.
4 * This file is from coreboot soc/intel/broadwell/include/soc/spi.h
6 * SPDX-License-Identifier: GPL-2.0
9 #ifndef _BROADWELL_SPI_H_
10 #define _BROADWELL_SPI_H_
13 * SPI Opcode Menu setup for SPIBAR lockdown
14 * should support most common flash chips.
17 #define SPIBAR_OFFSET 0x3800
18 #define SPI_REG(x) (RCB_REG(SPIBAR_OFFSET + (x)))
20 /* Reigsters within the SPIBAR */
21 #define SPIBAR_SSFC 0x91
22 #define SPIBAR_FDOC 0xb0
23 #define SPIBAR_FDOD 0xb4
25 #define SPIBAR_PREOP 0x94
26 #define SPIBAR_OPTYPE 0x96
27 #define SPIBAR_OPMENU_LOWER 0x98
28 #define SPIBAR_OPMENU_UPPER 0x9c
30 #define SPI_OPMENU_0 0x01 /* WRSR: Write Status Register */
31 #define SPI_OPTYPE_0 0x01 /* Write, no address */
33 #define SPI_OPMENU_1 0x02 /* BYPR: Byte Program */
34 #define SPI_OPTYPE_1 0x03 /* Write, address required */
36 #define SPI_OPMENU_2 0x03 /* READ: Read Data */
37 #define SPI_OPTYPE_2 0x02 /* Read, address required */
39 #define SPI_OPMENU_3 0x05 /* RDSR: Read Status Register */
40 #define SPI_OPTYPE_3 0x00 /* Read, no address */
42 #define SPI_OPMENU_4 0x20 /* SE20: Sector Erase 0x20 */
43 #define SPI_OPTYPE_4 0x03 /* Write, address required */
45 #define SPI_OPMENU_5 0x9f /* RDID: Read ID */
46 #define SPI_OPTYPE_5 0x00 /* Read, no address */
48 #define SPI_OPMENU_6 0xd8 /* BED8: Block Erase 0xd8 */
49 #define SPI_OPTYPE_6 0x03 /* Write, address required */
51 #define SPI_OPMENU_7 0x0b /* FAST: Fast Read */
52 #define SPI_OPTYPE_7 0x02 /* Read, address required */
54 #define SPI_OPMENU_UPPER ((SPI_OPMENU_7 << 24) | (SPI_OPMENU_6 << 16) | \
55 (SPI_OPMENU_5 << 8) | SPI_OPMENU_4)
56 #define SPI_OPMENU_LOWER ((SPI_OPMENU_3 << 24) | (SPI_OPMENU_2 << 16) | \
57 (SPI_OPMENU_1 << 8) | SPI_OPMENU_0)
59 #define SPI_OPTYPE ((SPI_OPTYPE_7 << 14) | (SPI_OPTYPE_6 << 12) | \
60 (SPI_OPTYPE_5 << 10) | (SPI_OPTYPE_4 << 8) | \
61 (SPI_OPTYPE_3 << 6) | (SPI_OPTYPE_2 << 4) | \
62 (SPI_OPTYPE_1 << 2) | (SPI_OPTYPE_0))
64 #define SPI_OPPREFIX ((0x50 << 8) | 0x06) /* EWSR and WREN */
66 #define SPIBAR_HSFS 0x04 /* SPI hardware sequence status */
67 #define SPIBAR_HSFS_FLOCKDN (1 << 15)/* Flash Configuration Lock-Down */
68 #define SPIBAR_HSFS_SCIP (1 << 5) /* SPI Cycle In Progress */
69 #define SPIBAR_HSFS_AEL (1 << 2) /* SPI Access Error Log */
70 #define SPIBAR_HSFS_FCERR (1 << 1) /* SPI Flash Cycle Error */
71 #define SPIBAR_HSFS_FDONE (1 << 0) /* SPI Flash Cycle Done */
72 #define SPIBAR_HSFC 0x06 /* SPI hardware sequence control */
73 #define SPIBAR_HSFC_BYTE_COUNT(c) (((c - 1) & 0x3f) << 8)
74 #define SPIBAR_HSFC_CYCLE_READ (0 << 1) /* Read cycle */
75 #define SPIBAR_HSFC_CYCLE_WRITE (2 << 1) /* Write cycle */
76 #define SPIBAR_HSFC_CYCLE_ERASE (3 << 1) /* Erase cycle */
77 #define SPIBAR_HSFC_GO (1 << 0) /* GO: start SPI transaction */
78 #define SPIBAR_FADDR 0x08 /* SPI flash address */
79 #define SPIBAR_FDATA(n) (0x10 + (4 * n)) /* SPI flash data */
80 #define SPIBAR_SSFS 0x90
81 #define SPIBAR_SSFS_ERROR (1 << 3)
82 #define SPIBAR_SSFS_DONE (1 << 2)
83 #define SPIBAR_SSFC 0x91
84 #define SPIBAR_SSFC_DATA (1 << 14)
85 #define SPIBAR_SSFC_GO (1 << 1)