1 /* SPDX-License-Identifier: Intel */
3 * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
6 #ifndef __FSP_CONFIGS_H__
7 #define __FSP_CONFIGS_H__
10 struct fsp_config_data {
11 struct fsp_cfg_common common;
12 struct upd_region fsp_upd;
15 struct fspinit_rtbuf {
16 struct common_buf common; /* FSP common runtime data structure */
20 /* FSP user configuration settings */
22 #define MRC_INIT_TSEG_SIZE_1MB 1
23 #define MRC_INIT_TSEG_SIZE_2MB 2
24 #define MRC_INIT_TSEG_SIZE_4MB 4
25 #define MRC_INIT_TSEG_SIZE_8MB 8
27 #define MRC_INIT_MMIO_SIZE_1024MB 0x400
28 #define MRC_INIT_MMIO_SIZE_1536MB 0x600
29 #define MRC_INIT_MMIO_SIZE_2048MB 0x800
31 #define EMMC_BOOT_MODE_DISABLED 0
32 #define EMMC_BOOT_MODE_AUTO 1
33 #define EMMC_BOOT_MODE_EMMC41 2
34 #define EMMC_BOOT_MODE_EMCC45 3
36 #define SATA_MODE_IDE 0
37 #define SATA_MODE_AHCI 1
39 #define IGD_DVMT50_PRE_ALLOC_32MB 0x01
40 #define IGD_DVMT50_PRE_ALLOC_64MB 0x02
41 #define IGD_DVMT50_PRE_ALLOC_96MB 0x03
42 #define IGD_DVMT50_PRE_ALLOC_128MB 0x04
43 #define IGD_DVMT50_PRE_ALLOC_160MB 0x05
44 #define IGD_DVMT50_PRE_ALLOC_192MB 0x06
45 #define IGD_DVMT50_PRE_ALLOC_224MB 0x07
46 #define IGD_DVMT50_PRE_ALLOC_256MB 0x08
47 #define IGD_DVMT50_PRE_ALLOC_288MB 0x09
48 #define IGD_DVMT50_PRE_ALLOC_320MB 0x0a
49 #define IGD_DVMT50_PRE_ALLOC_352MB 0x0b
50 #define IGD_DVMT50_PRE_ALLOC_384MB 0x0c
51 #define IGD_DVMT50_PRE_ALLOC_416MB 0x0d
52 #define IGD_DVMT50_PRE_ALLOC_448MB 0x0e
53 #define IGD_DVMT50_PRE_ALLOC_480MB 0x0f
54 #define IGD_DVMT50_PRE_ALLOC_512MB 0x10
56 #define APERTURE_SIZE_128MB 1
57 #define APERTURE_SIZE_256MB 2
58 #define APERTURE_SIZE_512MB 3
60 #define GTT_SIZE_1MB 1
61 #define GTT_SIZE_2MB 2
63 #define OS_SELECTION_ANDROID 1
64 #define OS_SELECTION_LINUX 4
66 #define DRAM_SPEED_800MTS 0
67 #define DRAM_SPEED_1066MTS 1
68 #define DRAM_SPEED_1333MTS 2
69 #define DRAM_SPEED_1600MTS 3
71 #define DRAM_TYPE_DDR3 0
72 #define DRAM_TYPE_DDR3L 1
73 #define DRAM_TYPE_DDR3ECC 2
74 #define DRAM_TYPE_LPDDR2 4
75 #define DRAM_TYPE_LPDDR3 5
76 #define DRAM_TYPE_DDR4 6
78 #define DIMM_WIDTH_X8 0
79 #define DIMM_WIDTH_X16 1
80 #define DIMM_WIDTH_X32 2
82 #define DIMM_DENSITY_1GBIT 0
83 #define DIMM_DENSITY_2GBIT 1
84 #define DIMM_DENSITY_4GBIT 2
85 #define DIMM_DENSITY_8GBIT 3
87 #define DIMM_BUS_WIDTH_8BITS 0
88 #define DIMM_BUS_WIDTH_16BITS 1
89 #define DIMM_BUS_WIDTH_32BITS 2
90 #define DIMM_BUS_WIDTH_64BITS 3
92 #define DIMM_SIDES_1RANKS 0
93 #define DIMM_SIDES_2RANKS 1
95 #define LPE_MODE_DISABLED 0
96 #define LPE_MODE_PCI 1
97 #define LPE_MODE_ACPI 2
99 #define LPSS_SIO_MODE_ACPI 0
100 #define LPSS_SIO_MODE_PCI 1
102 #define SCC_MODE_ACPI 0
103 #define SCC_MODE_PCI 1
105 #endif /* __FSP_CONFIGS_H__ */