1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2013 Google Inc.
4 * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
6 * Modified from coreboot src/soc/intel/baytrail/acpi/gpio.asl
9 /* SouthCluster GPIO */
16 Name(RBUF, ResourceTemplate()
18 Memory32Fixed(ReadWrite, 0, 0x1000, RMEM)
19 Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , ,)
27 CreateDwordField(^RBUF, ^RMEM._BAS, RBAS)
28 Add(IO_BASE_ADDRESS, IO_BASE_OFFSET_GPSCORE, RBAS)
38 /* NorthCluster GPIO */
45 Name(RBUF, ResourceTemplate()
47 Memory32Fixed(ReadWrite, 0, 0x1000, RMEM)
48 Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , ,)
56 CreateDwordField(^RBUF, ^RMEM._BAS, RBAS)
57 Add(IO_BASE_ADDRESS, IO_BASE_OFFSET_GPNCORE, RBAS)
74 Name(RBUF, ResourceTemplate()
76 Memory32Fixed(ReadWrite, 0, 0x1000, RMEM)
77 Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , ,)
85 CreateDwordField(^RBUF, ^RMEM._BAS, RBAS)
86 Add(IO_BASE_ADDRESS, IO_BASE_OFFSET_GPSSUS, RBAS)