1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2017 Intel Corporation.
4 * Take from coreboot project file of the same name
7 #ifndef _ASM_ARCH_IOMAP_H
8 #define _ASM_ARCH_IOMAP_H
10 #define R_ACPI_PM1_TMR 0x8
12 /* Put p2sb at 0xd0000000 in TPL */
13 #define IOMAP_P2SB_BAR 0xd0000000
15 #define IOMAP_SPI_BASE 0xfe010000
17 #define IOMAP_ACPI_BASE 0x400
18 #define IOMAP_ACPI_SIZE 0x100
21 * Use UART2. To use UART1 you need to set '2' to '1', change device tree serial
22 * node name and 'reg' property, and update CONFIG_DEBUG_UART_BASE.
24 #define PCH_DEV_UART PCI_BDF(0, 0x18, 2)
26 #define PCH_DEV_LPC PCI_BDF(0, 0x1f, 0)
27 #define PCH_DEV_SPI PCI_BDF(0, 0x0d, 2)