arch/x86/dts/u-boot.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2016 Google, Inc
   4  * Written by Simon Glass <sjg@chromium.org>
   5  */
   6
   7 #include <config.h>
   8
   9 #ifdef CONFIG_CHROMEOS
  10 / {
  11         binman {
  12                 multiple-images;
  13                 rom: rom {
  14                 };
  15         };
  16 };
  17 #else
  18 / {
  19         rom: binman {
  20         };
  21 };
  22 #endif
  23
  24 #ifdef CONFIG_ROM_SIZE
  25 &rom {
  26         filename = "u-boot.rom";
  27         end-at-4gb;
  28         sort-by-offset;
  29         pad-byte = <0xff>;
  30         size = <CONFIG_ROM_SIZE>;
  31 #ifdef CONFIG_HAVE_INTEL_ME
  32         intel-descriptor {
  33                 filename = CONFIG_FLASH_DESCRIPTOR_FILE;
  34         };
  35         intel-me {
  36                 filename = CONFIG_INTEL_ME_FILE;
  37         };
  38 #endif
  39 #ifdef CONFIG_TPL
  40 #ifdef CONFIG_HAVE_MICROCODE
  41         u-boot-tpl-with-ucode-ptr {
  42                 offset = <CONFIG_TPL_TEXT_BASE>;
  43         };
  44         u-boot-tpl-dtb {
  45         };
  46 #endif
  47         spl {
  48                 type = "section";
  49                 offset = <CONFIG_X86_OFFSET_SPL>;
  50                 u-boot-spl {
  51                 };
  52                 u-boot-spl-dtb {
  53                 };
  54         };
  55         u-boot {
  56                 type = "section";
  57                 offset = <CONFIG_X86_OFFSET_U_BOOT>;
  58                 u-boot-nodtb {
  59                 };
  60                 u-boot-dtb {
  61                 };
  62         };
  63 #elif defined(CONFIG_SPL)
  64         u-boot-spl-with-ucode-ptr {
  65                 offset = <CONFIG_X86_OFFSET_SPL>;
  66         };
  67         u-boot-dtb-with-ucode2 {
  68                 type = "u-boot-dtb-with-ucode";
  69         };
  70         u-boot {
  71                 offset = <CONFIG_X86_OFFSET_U_BOOT>;
  72         };
  73 #else
  74 # ifdef CONFIG_SPL
  75         u-boot {
  76                 offset = <CONFIG_SYS_TEXT_BASE>;
  77         };
  78 # else
  79         /* If there is no SPL then we need to put microcode in U-Boot */
  80         u-boot-with-ucode-ptr {
  81                 offset = <CONFIG_X86_OFFSET_U_BOOT>;
  82         };
  83 # endif
  84 #endif
  85 #ifdef CONFIG_HAVE_MICROCODE
  86         u-boot-dtb-with-ucode {
  87         };
  88         u-boot-ucode {
  89                 align = <16>;
  90         };
  91 #else
  92         u-boot-dtb {
  93         };
  94 #endif
  95 #ifdef CONFIG_HAVE_X86_FIT
  96         intel-fit {
  97         };
  98         intel-fit-ptr {
  99         };
 100 #endif
 101 #ifdef CONFIG_HAVE_MRC
 102         intel-mrc {
 103                 offset = <CONFIG_X86_MRC_ADDR>;
 104         };
 105 #endif
 106 #ifdef CONFIG_FSP_VERSION1
 107         intel-fsp {
 108                 filename = CONFIG_FSP_FILE;
 109                 offset = <CONFIG_FSP_ADDR>;
 110         };
 111 #endif
 112 #ifdef CONFIG_FSP_VERSION2
 113         intel-descriptor {
 114                 filename = CONFIG_FLASH_DESCRIPTOR_FILE;
 115         };
 116         intel-ifwi {
 117                 filename = CONFIG_IFWI_INPUT_FILE;
 118                 convert-fit;
 119
 120                 section {
 121                         size = <0x8000>;
 122                         ifwi-replace;
 123                         ifwi-subpart = "IBBP";
 124                         ifwi-entry = "IBBL";
 125                         u-boot-tpl {
 126                         };
 127                         x86-start16-tpl {
 128                                 offset = <0x7800>;
 129                         };
 130                         x86-reset16-tpl {
 131                                 offset = <0x7ff0>;
 132                         };
 133                 };
 134         };
 135         intel-fsp-m {
 136                 filename = CONFIG_FSP_FILE_M;
 137         };
 138         intel-fsp-s {
 139                 filename = CONFIG_FSP_FILE_S;
 140         };
 141 #endif
 142         fdtmap {
 143         };
 144 #ifdef CONFIG_HAVE_CMC
 145         intel-cmc {
 146                 filename = CONFIG_CMC_FILE;
 147                 offset = <CONFIG_CMC_ADDR>;
 148         };
 149 #endif
 150 #ifdef CONFIG_HAVE_VGA_BIOS
 151         intel-vga {
 152                 filename = CONFIG_VGA_BIOS_FILE;
 153                 offset = <CONFIG_VGA_BIOS_ADDR>;
 154         };
 155 #endif
 156 #ifdef CONFIG_HAVE_VBT
 157         intel-vbt {
 158                 filename = CONFIG_VBT_FILE;
 159                 offset = <CONFIG_VBT_ADDR>;
 160         };
 161 #endif
 162 #ifdef CONFIG_HAVE_REFCODE
 163         intel-refcode {
 164                 offset = <CONFIG_X86_REFCODE_ADDR>;
 165         };
 166 #endif
 167 #ifdef CONFIG_TPL
 168         x86-start16-tpl {
 169                 offset = <CONFIG_SYS_X86_START16>;
 170         };
 171         x86-reset16-tpl {
 172                 offset = <CONFIG_RESET_VEC_LOC>;
 173         };
 174 #elif defined(CONFIG_SPL)
 175         x86-start16-spl {
 176                 offset = <CONFIG_SYS_X86_START16>;
 177         };
 178         x86-reset16-spl {
 179                 offset = <CONFIG_RESET_VEC_LOC>;
 180         };
 181 #else
 182         x86-start16 {
 183                 offset = <CONFIG_SYS_X86_START16>;
 184         };
 185         x86-reset16 {
 186                 offset = <CONFIG_RESET_VEC_LOC>;
 187         };
 188 #endif
 189         image-header {
 190                 location = "end";
 191         };
 192 };
 193 #endif