1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2016 Google, Inc
4 * Written by Simon Glass <sjg@chromium.org>
12 filename = "u-boot.rom";
16 size = <CONFIG_ROM_SIZE>;
17 #ifdef CONFIG_HAVE_INTEL_ME
19 filename = CONFIG_FLASH_DESCRIPTOR_FILE;
22 filename = CONFIG_INTEL_ME_FILE;
26 u-boot-tpl-with-ucode-ptr {
27 offset = <CONFIG_TPL_TEXT_BASE>;
32 offset = <CONFIG_SPL_TEXT_BASE>;
37 offset = <CONFIG_SYS_TEXT_BASE>;
39 #elif defined(CONFIG_SPL)
40 u-boot-spl-with-ucode-ptr {
41 offset = <CONFIG_SPL_TEXT_BASE>;
44 u-boot-dtb-with-ucode2 {
45 type = "u-boot-dtb-with-ucode";
49 * TODO(sjg@chromium.org):
50 * Normally we use CONFIG_SYS_TEXT_BASE as the flash offset. But
51 * for boards with textbase in SDRAM we cannot do this. Just use
52 * an assumed-valid value (1MB before the end of flash) here so
53 * that we can actually build an image for coreboot, etc.
54 * We need a better solution, perhaps a separate Kconfig.
56 #if CONFIG_SYS_TEXT_BASE == 0x1110000
57 offset = <0xfff00000>;
59 offset = <CONFIG_SYS_TEXT_BASE>;
63 u-boot-with-ucode-ptr {
64 offset = <CONFIG_SYS_TEXT_BASE>;
67 u-boot-dtb-with-ucode {
72 #ifdef CONFIG_HAVE_MRC
74 offset = <CONFIG_X86_MRC_ADDR>;
77 #ifdef CONFIG_HAVE_FSP
79 filename = CONFIG_FSP_FILE;
80 offset = <CONFIG_FSP_ADDR>;
83 #ifdef CONFIG_HAVE_CMC
85 filename = CONFIG_CMC_FILE;
86 offset = <CONFIG_CMC_ADDR>;
89 #ifdef CONFIG_HAVE_VGA_BIOS
91 filename = CONFIG_VGA_BIOS_FILE;
92 offset = <CONFIG_VGA_BIOS_ADDR>;
95 #ifdef CONFIG_HAVE_VBT
97 filename = CONFIG_VBT_FILE;
98 offset = <CONFIG_VBT_ADDR>;
101 #ifdef CONFIG_HAVE_REFCODE
103 offset = <CONFIG_X86_REFCODE_ADDR>;
108 offset = <CONFIG_SYS_X86_START16>;
110 #elif defined(CONFIG_SPL)
112 offset = <CONFIG_SYS_X86_START16>;
116 offset = <CONFIG_SYS_X86_START16>;