x86: Update device tree for TPL
[oweals/u-boot.git] / arch / x86 / dts / u-boot.dtsi
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright (C) 2016 Google, Inc
4  * Written by Simon Glass <sjg@chromium.org>
5  */
6
7 #include <config.h>
8
9 #ifdef CONFIG_ROM_SIZE
10 / {
11         binman {
12                 filename = "u-boot.rom";
13                 end-at-4gb;
14                 sort-by-offset;
15                 pad-byte = <0xff>;
16                 size = <CONFIG_ROM_SIZE>;
17 #ifdef CONFIG_HAVE_INTEL_ME
18                 intel-descriptor {
19                         filename = CONFIG_FLASH_DESCRIPTOR_FILE;
20                 };
21                 intel-me {
22                         filename = CONFIG_INTEL_ME_FILE;
23                 };
24 #endif
25 #ifdef CONFIG_TPL
26                 u-boot-tpl-with-ucode-ptr {
27                         offset = <CONFIG_TPL_TEXT_BASE>;
28                 };
29                 u-boot-tpl-dtb {
30                 };
31                 u-boot-spl {
32                         offset = <CONFIG_SPL_TEXT_BASE>;
33                 };
34                 u-boot-spl-dtb {
35                 };
36                 u-boot {
37                         offset = <CONFIG_SYS_TEXT_BASE>;
38                 };
39 #elif defined(CONFIG_SPL)
40                 u-boot-spl-with-ucode-ptr {
41                         offset = <CONFIG_SPL_TEXT_BASE>;
42                 };
43
44                 u-boot-dtb-with-ucode2 {
45                         type = "u-boot-dtb-with-ucode";
46                 };
47                 u-boot {
48                 /*
49                  * TODO(sjg@chromium.org):
50                  * Normally we use CONFIG_SYS_TEXT_BASE as the flash offset. But
51                  * for boards with textbase in SDRAM we cannot do this. Just use
52                  * an assumed-valid value (1MB before the end of flash) here so
53                  * that we can actually build an image for coreboot, etc.
54                  * We need a better solution, perhaps a separate Kconfig.
55                  */
56 #if CONFIG_SYS_TEXT_BASE == 0x1110000
57                         offset = <0xfff00000>;
58 #else
59                         offset = <CONFIG_SYS_TEXT_BASE>;
60 #endif
61                 };
62 #else
63                 u-boot-with-ucode-ptr {
64                         offset = <CONFIG_SYS_TEXT_BASE>;
65                 };
66 #endif
67                 u-boot-dtb-with-ucode {
68                 };
69                 u-boot-ucode {
70                         align = <16>;
71                 };
72 #ifdef CONFIG_HAVE_MRC
73                 intel-mrc {
74                         offset = <CONFIG_X86_MRC_ADDR>;
75                 };
76 #endif
77 #ifdef CONFIG_HAVE_FSP
78                 intel-fsp {
79                         filename = CONFIG_FSP_FILE;
80                         offset = <CONFIG_FSP_ADDR>;
81                 };
82 #endif
83 #ifdef CONFIG_HAVE_CMC
84                 intel-cmc {
85                         filename = CONFIG_CMC_FILE;
86                         offset = <CONFIG_CMC_ADDR>;
87                 };
88 #endif
89 #ifdef CONFIG_HAVE_VGA_BIOS
90                 intel-vga {
91                         filename = CONFIG_VGA_BIOS_FILE;
92                         offset = <CONFIG_VGA_BIOS_ADDR>;
93                 };
94 #endif
95 #ifdef CONFIG_HAVE_VBT
96                 intel-vbt {
97                         filename = CONFIG_VBT_FILE;
98                         offset = <CONFIG_VBT_ADDR>;
99                 };
100 #endif
101 #ifdef CONFIG_HAVE_REFCODE
102                 intel-refcode {
103                         offset = <CONFIG_X86_REFCODE_ADDR>;
104                 };
105 #endif
106 #ifdef CONFIG_TPL
107                 x86-start16-tpl {
108                         offset = <CONFIG_SYS_X86_START16>;
109                 };
110 #elif defined(CONFIG_SPL)
111                 x86-start16-spl {
112                         offset = <CONFIG_SYS_X86_START16>;
113                 };
114 #else
115                 x86-start16 {
116                         offset = <CONFIG_SYS_X86_START16>;
117                 };
118 #endif
119         };
120 };
121 #endif