arch/x86/dts/u-boot.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2016 Google, Inc
   4  * Written by Simon Glass <sjg@chromium.org>
   5  */
   6
   7 #include <config.h>
   8
   9 #ifdef CONFIG_CHROMEOS
  10 / {
  11         binman {
  12                 multiple-images;
  13                 rom: rom {
  14                 };
  15         };
  16 };
  17 #else
  18 / {
  19         rom: binman {
  20         };
  21 };
  22 #endif
  23
  24 #ifdef CONFIG_ROM_SIZE
  25 &rom {
  26                 filename = "u-boot.rom";
  27                 end-at-4gb;
  28                 sort-by-offset;
  29                 pad-byte = <0xff>;
  30                 size = <CONFIG_ROM_SIZE>;
  31 #ifdef CONFIG_HAVE_INTEL_ME
  32                 intel-descriptor {
  33                         filename = CONFIG_FLASH_DESCRIPTOR_FILE;
  34                 };
  35                 intel-me {
  36                         filename = CONFIG_INTEL_ME_FILE;
  37                 };
  38 #endif
  39 #ifdef CONFIG_TPL
  40                 u-boot-tpl-with-ucode-ptr {
  41                         offset = <CONFIG_TPL_TEXT_BASE>;
  42                 };
  43                 u-boot-tpl-dtb {
  44                 };
  45                 u-boot-spl {
  46                         offset = <CONFIG_SPL_TEXT_BASE>;
  47                 };
  48                 u-boot-spl-dtb {
  49                 };
  50                 u-boot {
  51                         offset = <CONFIG_SYS_TEXT_BASE>;
  52                 };
  53 #elif defined(CONFIG_SPL)
  54                 u-boot-spl-with-ucode-ptr {
  55                         offset = <CONFIG_SPL_TEXT_BASE>;
  56                 };
  57
  58                 u-boot-dtb-with-ucode2 {
  59                         type = "u-boot-dtb-with-ucode";
  60                 };
  61                 u-boot {
  62                 /*
  63                  * TODO(sjg@chromium.org):
  64                  * Normally we use CONFIG_SYS_TEXT_BASE as the flash offset. But
  65                  * for boards with textbase in SDRAM we cannot do this. Just use
  66                  * an assumed-valid value (1MB before the end of flash) here so
  67                  * that we can actually build an image for coreboot, etc.
  68                  * We need a better solution, perhaps a separate Kconfig.
  69                  */
  70 #if CONFIG_SYS_TEXT_BASE == 0x1110000
  71                         offset = <0xfff00000>;
  72 #else
  73                         offset = <CONFIG_SYS_TEXT_BASE>;
  74 #endif
  75                 };
  76 #else
  77                 u-boot-with-ucode-ptr {
  78                         offset = <CONFIG_SYS_TEXT_BASE>;
  79                 };
  80 #endif
  81                 u-boot-dtb-with-ucode {
  82                 };
  83                 u-boot-ucode {
  84                         align = <16>;
  85                 };
  86 #ifdef CONFIG_HAVE_MRC
  87                 intel-mrc {
  88                         offset = <CONFIG_X86_MRC_ADDR>;
  89                 };
  90 #endif
  91 #ifdef CONFIG_HAVE_FSP
  92                 intel-fsp {
  93                         filename = CONFIG_FSP_FILE;
  94                         offset = <CONFIG_FSP_ADDR>;
  95                 };
  96 #endif
  97 #ifdef CONFIG_HAVE_CMC
  98                 intel-cmc {
  99                         filename = CONFIG_CMC_FILE;
 100                         offset = <CONFIG_CMC_ADDR>;
 101                 };
 102 #endif
 103 #ifdef CONFIG_HAVE_VGA_BIOS
 104                 intel-vga {
 105                         filename = CONFIG_VGA_BIOS_FILE;
 106                         offset = <CONFIG_VGA_BIOS_ADDR>;
 107                 };
 108 #endif
 109 #ifdef CONFIG_HAVE_VBT
 110                 intel-vbt {
 111                         filename = CONFIG_VBT_FILE;
 112                         offset = <CONFIG_VBT_ADDR>;
 113                 };
 114 #endif
 115 #ifdef CONFIG_HAVE_REFCODE
 116                 intel-refcode {
 117                         offset = <CONFIG_X86_REFCODE_ADDR>;
 118                 };
 119 #endif
 120 #ifdef CONFIG_TPL
 121                 x86-start16-tpl {
 122                         offset = <CONFIG_SYS_X86_START16>;
 123                 };
 124 #elif defined(CONFIG_SPL)
 125                 x86-start16-spl {
 126                         offset = <CONFIG_SYS_X86_START16>;
 127                 };
 128 #else
 129                 x86-start16 {
 130                         offset = <CONFIG_SYS_X86_START16>;
 131                 };
 132 #endif
 133 };
 134 #endif