arch/x86/dts/u-boot.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2016 Google, Inc
   4  * Written by Simon Glass <sjg@chromium.org>
   5  */
   6
   7 #include <config.h>
   8
   9 #ifdef CONFIG_CHROMEOS
  10 / {
  11         binman {
  12                 multiple-images;
  13                 rom: rom {
  14                 };
  15         };
  16 };
  17 #else
  18 / {
  19         rom: binman {
  20         };
  21 };
  22 #endif
  23
  24 #ifdef CONFIG_ROM_SIZE
  25 &rom {
  26         filename = "u-boot.rom";
  27         end-at-4gb;
  28         sort-by-offset;
  29         pad-byte = <0xff>;
  30         size = <CONFIG_ROM_SIZE>;
  31 #ifdef CONFIG_HAVE_INTEL_ME
  32         intel-descriptor {
  33                 filename = CONFIG_FLASH_DESCRIPTOR_FILE;
  34         };
  35         intel-me {
  36                 filename = CONFIG_INTEL_ME_FILE;
  37         };
  38 #endif
  39 #ifdef CONFIG_TPL
  40 #ifdef CONFIG_HAVE_MICROCODE
  41         u-boot-tpl-with-ucode-ptr {
  42                 offset = <CONFIG_TPL_TEXT_BASE>;
  43         };
  44         u-boot-tpl-dtb {
  45         };
  46 #endif
  47         u-boot-spl {
  48                 offset = <CONFIG_X86_OFFSET_SPL>;
  49         };
  50         u-boot-spl-dtb {
  51         };
  52         u-boot {
  53                 offset = <CONFIG_X86_OFFSET_U_BOOT>;
  54         };
  55 #elif defined(CONFIG_SPL)
  56         u-boot-spl-with-ucode-ptr {
  57                 offset = <CONFIG_X86_OFFSET_SPL>;
  58         };
  59         u-boot-dtb-with-ucode2 {
  60                 type = "u-boot-dtb-with-ucode";
  61         };
  62         u-boot {
  63                 offset = <CONFIG_X86_OFFSET_U_BOOT>;
  64         };
  65 #else
  66         u-boot-with-ucode-ptr {
  67                 offset = <CONFIG_X86_OFFSET_U_BOOT>;
  68         };
  69 #endif
  70 #ifdef CONFIG_HAVE_MICROCODE
  71         u-boot-dtb-with-ucode {
  72         };
  73         u-boot-ucode {
  74                 align = <16>;
  75         };
  76 #else
  77         u-boot-dtb {
  78         };
  79 #endif
  80 #ifdef CONFIG_HAVE_X86_FIT
  81         intel-fit {
  82         };
  83         intel-fit-ptr {
  84         };
  85 #endif
  86 #ifdef CONFIG_HAVE_MRC
  87         intel-mrc {
  88                 offset = <CONFIG_X86_MRC_ADDR>;
  89         };
  90 #endif
  91 #ifdef CONFIG_FSP_VERSION1
  92         intel-fsp {
  93                 filename = CONFIG_FSP_FILE;
  94                 offset = <CONFIG_FSP_ADDR>;
  95         };
  96 #endif
  97 #ifdef CONFIG_FSP_VERSION2
  98         intel-descriptor {
  99                 filename = CONFIG_FLASH_DESCRIPTOR_FILE;
 100         };
 101         intel-ifwi {
 102                 filename = CONFIG_IFWI_INPUT_FILE;
 103                 convert-fit;
 104
 105                 section {
 106                         size = <0x8000>;
 107                         ifwi-replace;
 108                         ifwi-subpart = "IBBP";
 109                         ifwi-entry = "IBBL";
 110                         u-boot-tpl {
 111                         };
 112                         x86-start16-tpl {
 113                                 offset = <0x7800>;
 114                         };
 115                         x86-reset16-tpl {
 116                                 offset = <0x7ff0>;
 117                         };
 118                 };
 119         };
 120         intel-fsp-m {
 121                 filename = CONFIG_FSP_FILE_M;
 122         };
 123         intel-fsp-s {
 124                 filename = CONFIG_FSP_FILE_S;
 125         };
 126 #endif
 127         fdtmap {
 128         };
 129 #ifdef CONFIG_HAVE_CMC
 130         intel-cmc {
 131                 filename = CONFIG_CMC_FILE;
 132                 offset = <CONFIG_CMC_ADDR>;
 133         };
 134 #endif
 135 #ifdef CONFIG_HAVE_VGA_BIOS
 136         intel-vga {
 137                 filename = CONFIG_VGA_BIOS_FILE;
 138                 offset = <CONFIG_VGA_BIOS_ADDR>;
 139         };
 140 #endif
 141 #ifdef CONFIG_HAVE_VBT
 142         intel-vbt {
 143                 filename = CONFIG_VBT_FILE;
 144                 offset = <CONFIG_VBT_ADDR>;
 145         };
 146 #endif
 147 #ifdef CONFIG_HAVE_REFCODE
 148         intel-refcode {
 149                 offset = <CONFIG_X86_REFCODE_ADDR>;
 150         };
 151 #endif
 152 #ifdef CONFIG_TPL
 153         x86-start16-tpl {
 154                 offset = <CONFIG_SYS_X86_START16>;
 155         };
 156         x86-reset16-tpl {
 157                 offset = <CONFIG_RESET_VEC_LOC>;
 158         };
 159 #elif defined(CONFIG_SPL)
 160         x86-start16-spl {
 161                 offset = <CONFIG_SYS_X86_START16>;
 162         };
 163         x86-reset16-spl {
 164                 offset = <CONFIG_RESET_VEC_LOC>;
 165         };
 166 #else
 167         x86-start16 {
 168                 offset = <CONFIG_SYS_X86_START16>;
 169         };
 170         x86-reset16 {
 171                 offset = <CONFIG_RESET_VEC_LOC>;
 172         };
 173 #endif
 174         image-header {
 175                 location = "end";
 176         };
 177 };
 178 #endif