arch/x86/dts/u-boot.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2016 Google, Inc
   4  * Written by Simon Glass <sjg@chromium.org>
   5  */
   6
   7 #include <config.h>
   8
   9 #ifdef CONFIG_ROM_SIZE
  10 / {
  11         binman {
  12                 filename = "u-boot.rom";
  13                 end-at-4gb;
  14                 sort-by-offset;
  15                 pad-byte = <0xff>;
  16                 size = <CONFIG_ROM_SIZE>;
  17 #ifdef CONFIG_HAVE_INTEL_ME
  18                 intel-descriptor {
  19                         filename = CONFIG_FLASH_DESCRIPTOR_FILE;
  20                 };
  21                 intel-me {
  22                         filename = CONFIG_INTEL_ME_FILE;
  23                 };
  24 #endif
  25 #ifdef CONFIG_SPL
  26                 u-boot-spl-with-ucode-ptr {
  27                         offset = <CONFIG_SPL_TEXT_BASE>;
  28                 };
  29
  30                 u-boot-dtb-with-ucode2 {
  31                         type = "u-boot-dtb-with-ucode";
  32                 };
  33                 u-boot {
  34                         offset = <0xfff00000>;
  35                 };
  36 #else
  37                 u-boot-with-ucode-ptr {
  38                         offset = <CONFIG_SYS_TEXT_BASE>;
  39                 };
  40 #endif
  41                 u-boot-dtb-with-ucode {
  42                 };
  43                 u-boot-ucode {
  44                         align = <16>;
  45                 };
  46 #ifdef CONFIG_HAVE_MRC
  47                 intel-mrc {
  48                         offset = <CONFIG_X86_MRC_ADDR>;
  49                 };
  50 #endif
  51 #ifdef CONFIG_HAVE_FSP
  52                 intel-fsp {
  53                         filename = CONFIG_FSP_FILE;
  54                         offset = <CONFIG_FSP_ADDR>;
  55                 };
  56 #endif
  57 #ifdef CONFIG_HAVE_CMC
  58                 intel-cmc {
  59                         filename = CONFIG_CMC_FILE;
  60                         offset = <CONFIG_CMC_ADDR>;
  61                 };
  62 #endif
  63 #ifdef CONFIG_HAVE_VGA_BIOS
  64                 intel-vga {
  65                         filename = CONFIG_VGA_BIOS_FILE;
  66                         offset = <CONFIG_VGA_BIOS_ADDR>;
  67                 };
  68 #endif
  69 #ifdef CONFIG_HAVE_VBT
  70                 intel-vbt {
  71                         filename = CONFIG_VBT_FILE;
  72                         offset = <CONFIG_VBT_ADDR>;
  73                 };
  74 #endif
  75 #ifdef CONFIG_HAVE_REFCODE
  76                 intel-refcode {
  77                         offset = <CONFIG_X86_REFCODE_ADDR>;
  78                 };
  79 #endif
  80 #ifdef CONFIG_SPL
  81                 x86-start16-spl {
  82                         offset = <CONFIG_SYS_X86_START16>;
  83                 };
  84 #else
  85                 x86-start16 {
  86                         offset = <CONFIG_SYS_X86_START16>;
  87                 };
  88 #endif
  89         };
  90 };
  91 #endif