1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2016 Google, Inc
4 * Written by Simon Glass <sjg@chromium.org>
24 #ifdef CONFIG_ROM_SIZE
26 filename = "u-boot.rom";
30 size = <CONFIG_ROM_SIZE>;
31 #ifdef CONFIG_HAVE_INTEL_ME
33 filename = CONFIG_FLASH_DESCRIPTOR_FILE;
36 filename = CONFIG_INTEL_ME_FILE;
40 u-boot-tpl-with-ucode-ptr {
41 offset = <CONFIG_TPL_TEXT_BASE>;
46 offset = <CONFIG_SPL_TEXT_BASE>;
51 offset = <CONFIG_SYS_TEXT_BASE>;
53 #elif defined(CONFIG_SPL)
54 u-boot-spl-with-ucode-ptr {
55 offset = <CONFIG_SPL_TEXT_BASE>;
57 u-boot-dtb-with-ucode2 {
58 type = "u-boot-dtb-with-ucode";
62 * TODO(sjg@chromium.org):
63 * Normally we use CONFIG_SYS_TEXT_BASE as the flash offset. But
64 * for boards with textbase in SDRAM we cannot do this. Just use
65 * an assumed-valid value (1MB before the end of flash) here so
66 * that we can actually build an image for coreboot, etc.
67 * We need a better solution, perhaps a separate Kconfig.
69 #if CONFIG_SYS_TEXT_BASE == 0x1110000
70 offset = <0xfff00000>;
72 offset = <CONFIG_SYS_TEXT_BASE>;
76 u-boot-with-ucode-ptr {
77 offset = <CONFIG_SYS_TEXT_BASE>;
80 u-boot-dtb-with-ucode {
85 #ifdef CONFIG_HAVE_MRC
87 offset = <CONFIG_X86_MRC_ADDR>;
90 #ifdef CONFIG_HAVE_FSP
92 filename = CONFIG_FSP_FILE;
93 offset = <CONFIG_FSP_ADDR>;
96 #ifdef CONFIG_HAVE_CMC
98 filename = CONFIG_CMC_FILE;
99 offset = <CONFIG_CMC_ADDR>;
102 #ifdef CONFIG_HAVE_VGA_BIOS
104 filename = CONFIG_VGA_BIOS_FILE;
105 offset = <CONFIG_VGA_BIOS_ADDR>;
108 #ifdef CONFIG_HAVE_VBT
110 filename = CONFIG_VBT_FILE;
111 offset = <CONFIG_VBT_ADDR>;
114 #ifdef CONFIG_HAVE_REFCODE
116 offset = <CONFIG_X86_REFCODE_ADDR>;
121 offset = <CONFIG_SYS_X86_START16>;
124 offset = <CONFIG_RESET_VEC_LOC>;
126 #elif defined(CONFIG_SPL)
128 offset = <CONFIG_SYS_X86_START16>;
131 offset = <CONFIG_RESET_VEC_LOC>;
135 offset = <CONFIG_SYS_X86_START16>;
138 offset = <CONFIG_RESET_VEC_LOC>;