arch/x86/dts/u-boot.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2016 Google, Inc
   4  * Written by Simon Glass <sjg@chromium.org>
   5  */
   6
   7 #include <config.h>
   8
   9 #ifdef CONFIG_CHROMEOS
  10 / {
  11         binman {
  12                 multiple-images;
  13                 rom: rom {
  14                 };
  15         };
  16 };
  17 #else
  18 / {
  19         rom: binman {
  20         };
  21 };
  22 #endif
  23
  24 #ifdef CONFIG_ROM_SIZE
  25 &rom {
  26         filename = "u-boot.rom";
  27         end-at-4gb;
  28         sort-by-offset;
  29         pad-byte = <0xff>;
  30         size = <CONFIG_ROM_SIZE>;
  31 #ifdef CONFIG_HAVE_INTEL_ME
  32         intel-descriptor {
  33                 filename = CONFIG_FLASH_DESCRIPTOR_FILE;
  34         };
  35         intel-me {
  36                 filename = CONFIG_INTEL_ME_FILE;
  37         };
  38 #endif
  39 #ifdef CONFIG_TPL
  40         u-boot-tpl-with-ucode-ptr {
  41                 offset = <CONFIG_TPL_TEXT_BASE>;
  42         };
  43         u-boot-tpl-dtb {
  44         };
  45         u-boot-spl {
  46                 offset = <CONFIG_SPL_TEXT_BASE>;
  47         };
  48         u-boot-spl-dtb {
  49         };
  50         u-boot {
  51                 offset = <CONFIG_SYS_TEXT_BASE>;
  52         };
  53 #elif defined(CONFIG_SPL)
  54         u-boot-spl-with-ucode-ptr {
  55                 offset = <CONFIG_SPL_TEXT_BASE>;
  56         };
  57         u-boot-dtb-with-ucode2 {
  58                 type = "u-boot-dtb-with-ucode";
  59         };
  60         u-boot {
  61                 /*
  62                  * TODO(sjg@chromium.org):
  63                  * Normally we use CONFIG_SYS_TEXT_BASE as the flash offset. But
  64                  * for boards with textbase in SDRAM we cannot do this. Just use
  65                  * an assumed-valid value (1MB before the end of flash) here so
  66                  * that we can actually build an image for coreboot, etc.
  67                  * We need a better solution, perhaps a separate Kconfig.
  68                  */
  69 #if CONFIG_SYS_TEXT_BASE == 0x1110000
  70                 offset = <0xfff00000>;
  71 #else
  72                 offset = <CONFIG_SYS_TEXT_BASE>;
  73 #endif
  74         };
  75 #else
  76         u-boot-with-ucode-ptr {
  77                 offset = <CONFIG_SYS_TEXT_BASE>;
  78         };
  79 #endif
  80         u-boot-dtb-with-ucode {
  81         };
  82         u-boot-ucode {
  83                 align = <16>;
  84         };
  85 #ifdef CONFIG_HAVE_MRC
  86         intel-mrc {
  87                 offset = <CONFIG_X86_MRC_ADDR>;
  88         };
  89 #endif
  90 #ifdef CONFIG_HAVE_FSP
  91         intel-fsp {
  92                 filename = CONFIG_FSP_FILE;
  93                 offset = <CONFIG_FSP_ADDR>;
  94         };
  95 #endif
  96 #ifdef CONFIG_HAVE_CMC
  97         intel-cmc {
  98                 filename = CONFIG_CMC_FILE;
  99                 offset = <CONFIG_CMC_ADDR>;
 100         };
 101 #endif
 102 #ifdef CONFIG_HAVE_VGA_BIOS
 103         intel-vga {
 104                 filename = CONFIG_VGA_BIOS_FILE;
 105                 offset = <CONFIG_VGA_BIOS_ADDR>;
 106         };
 107 #endif
 108 #ifdef CONFIG_HAVE_VBT
 109         intel-vbt {
 110                 filename = CONFIG_VBT_FILE;
 111                 offset = <CONFIG_VBT_ADDR>;
 112         };
 113 #endif
 114 #ifdef CONFIG_HAVE_REFCODE
 115         intel-refcode {
 116                 offset = <CONFIG_X86_REFCODE_ADDR>;
 117         };
 118 #endif
 119 #ifdef CONFIG_TPL
 120         x86-start16-tpl {
 121                 offset = <CONFIG_SYS_X86_START16>;
 122         };
 123         x86-reset16-tpl {
 124                 offset = <CONFIG_RESET_VEC_LOC>;
 125         };
 126 #elif defined(CONFIG_SPL)
 127         x86-start16-spl {
 128                 offset = <CONFIG_SYS_X86_START16>;
 129         };
 130         x86-reset16-spl {
 131                 offset = <CONFIG_RESET_VEC_LOC>;
 132         };
 133 #else
 134         x86-start16 {
 135                 offset = <CONFIG_SYS_X86_START16>;
 136         };
 137         x86-reset16 {
 138                 offset = <CONFIG_RESET_VEC_LOC>;
 139         };
 140 #endif
 141 };
 142 #endif