2 * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
4 * SPDX-License-Identifier: GPL-2.0+
9 #include <dt-bindings/gpio/x86-gpio.h>
10 #include <dt-bindings/interrupt-router/intel-irq.h>
12 /include/ "skeleton.dtsi"
13 /include/ "serial.dtsi"
17 model = "Intel Minnowboard Max";
18 compatible = "intel,minnowmax", "intel,baytrail";
30 compatible = "intel,x86-pinctrl";
34 gpio-offset = <0x80 8>;
38 direction = <PIN_OUTPUT>;
42 gpio-offset = <0x80 9>;
46 direction = <PIN_OUTPUT>;
51 compatible = "intel,ich6-gpio";
58 compatible = "intel,ich6-gpio";
65 compatible = "intel,ich6-gpio";
72 compatible = "intel,ich6-gpio";
79 compatible = "intel,ich6-gpio";
86 compatible = "intel,ich6-gpio";
93 stdout-path = "/serial";
102 compatible = "intel,baytrail-cpu";
109 compatible = "intel,baytrail-cpu";
117 compatible = "intel,pci-baytrail", "pci-x86";
118 #address-cells = <3>;
121 ranges = <0x02000000 0x0 0x80000000 0x80000000 0 0x40000000
122 0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000
123 0x01000000 0x0 0x2000 0x2000 0 0xe000>;
126 reg = <0x0000f800 0 0 0 0>;
127 compatible = "intel,irq-router";
128 intel,pirq-config = "ibase";
129 intel,ibase-offset = <0x50>;
130 intel,pirq-link = <8 8>;
131 intel,pirq-mask = <0xdee0>;
132 intel,pirq-routing = <
133 /* BayTrail PCI devices */
134 PCI_BDF(0, 2, 0) INTA PIRQA
135 PCI_BDF(0, 3, 0) INTA PIRQA
136 PCI_BDF(0, 16, 0) INTA PIRQA
137 PCI_BDF(0, 17, 0) INTA PIRQA
138 PCI_BDF(0, 18, 0) INTA PIRQA
139 PCI_BDF(0, 19, 0) INTA PIRQA
140 PCI_BDF(0, 20, 0) INTA PIRQA
141 PCI_BDF(0, 21, 0) INTA PIRQA
142 PCI_BDF(0, 22, 0) INTA PIRQA
143 PCI_BDF(0, 23, 0) INTA PIRQA
144 PCI_BDF(0, 24, 0) INTA PIRQA
145 PCI_BDF(0, 24, 1) INTC PIRQC
146 PCI_BDF(0, 24, 2) INTD PIRQD
147 PCI_BDF(0, 24, 3) INTB PIRQB
148 PCI_BDF(0, 24, 4) INTA PIRQA
149 PCI_BDF(0, 24, 5) INTC PIRQC
150 PCI_BDF(0, 24, 6) INTD PIRQD
151 PCI_BDF(0, 24, 7) INTB PIRQB
152 PCI_BDF(0, 26, 0) INTA PIRQA
153 PCI_BDF(0, 27, 0) INTA PIRQA
154 PCI_BDF(0, 28, 0) INTA PIRQA
155 PCI_BDF(0, 28, 1) INTB PIRQB
156 PCI_BDF(0, 28, 2) INTC PIRQC
157 PCI_BDF(0, 28, 3) INTD PIRQD
158 PCI_BDF(0, 29, 0) INTA PIRQA
159 PCI_BDF(0, 30, 0) INTA PIRQA
160 PCI_BDF(0, 30, 1) INTD PIRQD
161 PCI_BDF(0, 30, 2) INTB PIRQB
162 PCI_BDF(0, 30, 3) INTC PIRQC
163 PCI_BDF(0, 30, 4) INTD PIRQD
164 PCI_BDF(0, 30, 5) INTB PIRQB
165 PCI_BDF(0, 31, 3) INTB PIRQB
167 /* PCIe root ports downstream interrupts */
168 PCI_BDF(1, 0, 0) INTA PIRQA
169 PCI_BDF(1, 0, 0) INTB PIRQB
170 PCI_BDF(1, 0, 0) INTC PIRQC
171 PCI_BDF(1, 0, 0) INTD PIRQD
172 PCI_BDF(2, 0, 0) INTA PIRQB
173 PCI_BDF(2, 0, 0) INTB PIRQC
174 PCI_BDF(2, 0, 0) INTC PIRQD
175 PCI_BDF(2, 0, 0) INTD PIRQA
176 PCI_BDF(3, 0, 0) INTA PIRQC
177 PCI_BDF(3, 0, 0) INTB PIRQD
178 PCI_BDF(3, 0, 0) INTC PIRQA
179 PCI_BDF(3, 0, 0) INTD PIRQB
180 PCI_BDF(4, 0, 0) INTA PIRQD
181 PCI_BDF(4, 0, 0) INTB PIRQA
182 PCI_BDF(4, 0, 0) INTC PIRQB
183 PCI_BDF(4, 0, 0) INTD PIRQC
189 compatible = "intel,baytrail-fsp";
190 fsp,mrc-init-tseg-size = <0>;
191 fsp,mrc-init-mmio-size = <0x800>;
192 fsp,mrc-init-spd-addr1 = <0xa0>;
193 fsp,mrc-init-spd-addr2 = <0xa2>;
194 fsp,emmc-boot-mode = <2>;
202 fsp,lpss-sio-enable-pci-mode;
214 fsp,igd-dvmt50-pre-alloc = <2>;
215 fsp,aperture-size = <2>;
217 fsp,serial-debug-port-address = <0x3f8>;
218 fsp,serial-debug-port-type = <1>;
219 fsp,scc-enable-pci-mode;
220 fsp,os-selection = <4>;
221 fsp,emmc45-ddr50-enabled;
222 fsp,emmc45-retune-timer-value = <8>;
224 fsp,enable-memory-down;
225 fsp,memory-down-params {
226 compatible = "intel,baytrail-fsp-mdp";
227 fsp,dram-speed = <1>;
230 fsp,dimm-width = <1>;
231 fsp,dimm-density = <2>;
232 fsp,dimm-bus-width = <3>;
233 fsp,dimm-sides = <0>;
234 fsp,dimm-tcl = <0xb>;
235 fsp,dimm-trpt-rcd = <0xb>;
236 fsp,dimm-twr = <0xc>;
240 fsp,dimm-tfaw = <0x14>;
245 #address-cells = <1>;
247 compatible = "intel,ich-spi";
250 compatible = "stmicro,n25q064a", "spi-flash";
251 memory-map = <0xff800000 0x00800000>;
257 #include "microcode/m0130673322.dtsi"