2 * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
4 * SPDX-License-Identifier: GPL-2.0+
9 #include <dt-bindings/gpio/x86-gpio.h>
10 #include <dt-bindings/interrupt-router/intel-irq.h>
12 /include/ "skeleton.dtsi"
13 /include/ "serial.dtsi"
17 model = "Intel Minnowboard Max";
18 compatible = "intel,minnowmax", "intel,baytrail";
30 compatible = "intel,x86-pinctrl";
35 gpio-offset = <0x80 0>;
39 direction = <PIN_OUTPUT>;
44 gpio-offset = <0x80 1>;
48 direction = <PIN_OUTPUT>;
53 gpio-offset = <0x80 2>;
57 direction = <PIN_OUTPUT>;
61 gpio-offset = <0x80 8>;
65 direction = <PIN_OUTPUT>;
69 gpio-offset = <0x80 9>;
73 direction = <PIN_OUTPUT>;
78 compatible = "intel,ich6-gpio";
85 compatible = "intel,ich6-gpio";
92 compatible = "intel,ich6-gpio";
99 compatible = "intel,ich6-gpio";
106 compatible = "intel,ich6-gpio";
113 compatible = "intel,ich6-gpio";
120 stdout-path = "/serial";
124 #address-cells = <1>;
129 compatible = "intel,baytrail-cpu";
136 compatible = "intel,baytrail-cpu";
144 compatible = "intel,pci-baytrail", "pci-x86";
145 #address-cells = <3>;
148 ranges = <0x02000000 0x0 0x80000000 0x80000000 0 0x40000000
149 0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000
150 0x01000000 0x0 0x2000 0x2000 0 0xe000>;
153 reg = <0x0000f800 0 0 0 0>;
154 compatible = "intel,irq-router";
155 intel,pirq-config = "ibase";
156 intel,ibase-offset = <0x50>;
157 intel,pirq-link = <8 8>;
158 intel,pirq-mask = <0xdee0>;
159 intel,pirq-routing = <
160 /* BayTrail PCI devices */
161 PCI_BDF(0, 2, 0) INTA PIRQA
162 PCI_BDF(0, 3, 0) INTA PIRQA
163 PCI_BDF(0, 16, 0) INTA PIRQA
164 PCI_BDF(0, 17, 0) INTA PIRQA
165 PCI_BDF(0, 18, 0) INTA PIRQA
166 PCI_BDF(0, 19, 0) INTA PIRQA
167 PCI_BDF(0, 20, 0) INTA PIRQA
168 PCI_BDF(0, 21, 0) INTA PIRQA
169 PCI_BDF(0, 22, 0) INTA PIRQA
170 PCI_BDF(0, 23, 0) INTA PIRQA
171 PCI_BDF(0, 24, 0) INTA PIRQA
172 PCI_BDF(0, 24, 1) INTC PIRQC
173 PCI_BDF(0, 24, 2) INTD PIRQD
174 PCI_BDF(0, 24, 3) INTB PIRQB
175 PCI_BDF(0, 24, 4) INTA PIRQA
176 PCI_BDF(0, 24, 5) INTC PIRQC
177 PCI_BDF(0, 24, 6) INTD PIRQD
178 PCI_BDF(0, 24, 7) INTB PIRQB
179 PCI_BDF(0, 26, 0) INTA PIRQA
180 PCI_BDF(0, 27, 0) INTA PIRQA
181 PCI_BDF(0, 28, 0) INTA PIRQA
182 PCI_BDF(0, 28, 1) INTB PIRQB
183 PCI_BDF(0, 28, 2) INTC PIRQC
184 PCI_BDF(0, 28, 3) INTD PIRQD
185 PCI_BDF(0, 29, 0) INTA PIRQA
186 PCI_BDF(0, 30, 0) INTA PIRQA
187 PCI_BDF(0, 30, 1) INTD PIRQD
188 PCI_BDF(0, 30, 2) INTB PIRQB
189 PCI_BDF(0, 30, 3) INTC PIRQC
190 PCI_BDF(0, 30, 4) INTD PIRQD
191 PCI_BDF(0, 30, 5) INTB PIRQB
192 PCI_BDF(0, 31, 3) INTB PIRQB
194 /* PCIe root ports downstream interrupts */
195 PCI_BDF(1, 0, 0) INTA PIRQA
196 PCI_BDF(1, 0, 0) INTB PIRQB
197 PCI_BDF(1, 0, 0) INTC PIRQC
198 PCI_BDF(1, 0, 0) INTD PIRQD
199 PCI_BDF(2, 0, 0) INTA PIRQB
200 PCI_BDF(2, 0, 0) INTB PIRQC
201 PCI_BDF(2, 0, 0) INTC PIRQD
202 PCI_BDF(2, 0, 0) INTD PIRQA
203 PCI_BDF(3, 0, 0) INTA PIRQC
204 PCI_BDF(3, 0, 0) INTB PIRQD
205 PCI_BDF(3, 0, 0) INTC PIRQA
206 PCI_BDF(3, 0, 0) INTD PIRQB
207 PCI_BDF(4, 0, 0) INTA PIRQD
208 PCI_BDF(4, 0, 0) INTB PIRQA
209 PCI_BDF(4, 0, 0) INTC PIRQB
210 PCI_BDF(4, 0, 0) INTD PIRQC
216 compatible = "intel,baytrail-fsp";
217 fsp,mrc-init-tseg-size = <0>;
218 fsp,mrc-init-mmio-size = <0x800>;
219 fsp,mrc-init-spd-addr1 = <0xa0>;
220 fsp,mrc-init-spd-addr2 = <0xa2>;
221 fsp,emmc-boot-mode = <2>;
229 fsp,lpss-sio-enable-pci-mode;
241 fsp,igd-dvmt50-pre-alloc = <2>;
242 fsp,aperture-size = <2>;
244 fsp,serial-debug-port-address = <0x3f8>;
245 fsp,serial-debug-port-type = <1>;
246 fsp,scc-enable-pci-mode;
247 fsp,os-selection = <4>;
248 fsp,emmc45-ddr50-enabled;
249 fsp,emmc45-retune-timer-value = <8>;
251 fsp,enable-memory-down;
252 fsp,memory-down-params {
253 compatible = "intel,baytrail-fsp-mdp";
254 fsp,dram-speed = <1>;
257 fsp,dimm-width = <1>;
258 fsp,dimm-density = <2>;
259 fsp,dimm-bus-width = <3>;
260 fsp,dimm-sides = <0>;
261 fsp,dimm-tcl = <0xb>;
262 fsp,dimm-trpt-rcd = <0xb>;
263 fsp,dimm-twr = <0xc>;
267 fsp,dimm-tfaw = <0x14>;
272 #address-cells = <1>;
274 compatible = "intel,ich-spi";
277 compatible = "stmicro,n25q064a", "spi-flash";
278 memory-map = <0xff800000 0x00800000>;
284 #include "microcode/m0130673322.dtsi"
287 #include "microcode/m0130679901.dtsi"