2 * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
4 * SPDX-License-Identifier: GPL-2.0+
9 #include <dt-bindings/gpio/x86-gpio.h>
11 /include/ "skeleton.dtsi"
12 /include/ "serial.dtsi"
16 model = "Intel Minnowboard Max";
17 compatible = "intel,minnowmax", "intel,baytrail";
29 compatible = "intel,x86-pinctrl";
33 gpio-offset = <0x80 8>;
37 direction = <PIN_OUTPUT>;
41 gpio-offset = <0x80 9>;
45 direction = <PIN_OUTPUT>;
50 compatible = "intel,ich6-gpio";
57 compatible = "intel,ich6-gpio";
64 compatible = "intel,ich6-gpio";
71 compatible = "intel,ich6-gpio";
78 compatible = "intel,ich6-gpio";
85 compatible = "intel,ich6-gpio";
92 stdout-path = "/serial";
101 compatible = "intel,baytrail-cpu";
108 compatible = "intel,baytrail-cpu";
116 compatible = "intel,pci-baytrail", "pci-x86";
117 #address-cells = <3>;
120 ranges = <0x02000000 0x0 0xd0000000 0xd0000000 0 0x10000000
121 0x42000000 0x0 0xc0000000 0xc0000000 0 0x10000000
122 0x01000000 0x0 0x2000 0x2000 0 0xe000>;
126 compatible = "intel,baytrail-fsp";
127 fsp,mrc-init-tseg-size = <0>;
128 fsp,mrc-init-mmio-size = <0x800>;
129 fsp,mrc-init-spd-addr1 = <0xa0>;
130 fsp,mrc-init-spd-addr2 = <0xa2>;
131 fsp,emmc-boot-mode = <2>;
139 fsp,lpss-sio-enable-pci-mode;
151 fsp,igd-dvmt50-pre-alloc = <2>;
152 fsp,aperture-size = <2>;
154 fsp,serial-debug-port-address = <0x3f8>;
155 fsp,serial-debug-port-type = <1>;
156 fsp,scc-enable-pci-mode;
157 fsp,os-selection = <4>;
158 fsp,emmc45-ddr50-enabled;
159 fsp,emmc45-retune-timer-value = <8>;
161 fsp,enable-memory-down;
162 fsp,memory-down-params {
163 compatible = "intel,baytrail-fsp-mdp";
164 fsp,dram-speed = <1>;
167 fsp,dimm-width = <1>;
168 fsp,dimm-density = <2>;
169 fsp,dimm-bus-width = <3>;
170 fsp,dimm-sides = <0>;
171 fsp,dimm-tcl = <0xb>;
172 fsp,dimm-trpt-rcd = <0xb>;
173 fsp,dimm-twr = <0xc>;
177 fsp,dimm-tfaw = <0x14>;
182 #address-cells = <1>;
184 compatible = "intel,ich-spi";
187 compatible = "stmicro,n25q064a", "spi-flash";
188 memory-map = <0xff800000 0x00800000>;
194 #include "microcode/m0130673322.dtsi"