3 /include/ "coreboot.dtsi"
9 compatible = "google,link", "intel,celeron-ivybridge";
19 clock-frequency = <115200>;
23 memory { device_type = "memory"; reg = <0 0>; };
28 compatible = "intel,ich9";
31 compatible = "winbond,w25q64", "spi-flash";
32 memory-map = <0xff800000 0x00800000>;
37 compatible = "intel,lpc";
41 compatible = "google,cros-ec";
42 reg = <0x204 1 0x200 1 0x880 0x80>;
44 /* This describes the flash memory within the EC */
48 reg = <0x08000000 0x20000>;