1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
4 * Copyright (C) 2016 Stefan Roese <sr@denx.de>
7 #include <asm/arch-baytrail/fsp/fsp_configs.h>
8 #include <dt-bindings/gpio/x86-gpio.h>
9 #include <dt-bindings/interrupt-router/intel-irq.h>
11 #include "skeleton.dtsi"
13 #include "tsc_timer.dtsi"
21 compatible = "intel,x86-pinctrl";
24 /* Add UART1 PAD configuration (SIO HS-UART) */
36 * As of today, the latest version FSP (gold4) for BayTrail
37 * misses the PAD configuration of the SD controller's Card
38 * Detect signal. The default PAD value for the CD pin sets
39 * the pin to work in GPIO mode, which causes card detect
40 * status cannot be reflected by the Present State register
41 * in the SD controller (bit 16 & bit 18 are always zero).
43 * Configure this pin to function 1 (SD controller).
50 xhci_hub_reset: usb_ulpi_stp@0 {
51 gpio-offset = <0xa0 10>;
52 pad-offset = <0x23b0>;
56 direction = <PIN_OUTPUT>;
61 stdout-path = "/serial";
70 compatible = "intel,baytrail-cpu";
77 compatible = "intel,baytrail-cpu";
84 compatible = "intel,baytrail-cpu";
91 compatible = "intel,baytrail-cpu";
98 compatible = "intel,pci-baytrail", "pci-x86";
102 ranges = <0x02000000 0x0 0x80000000 0x80000000 0 0x40000000
103 0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000
104 0x01000000 0x0 0x2000 0x2000 0 0xe000>;
106 pciuart0: uart@1e,3 {
107 compatible = "pci8086,0f0a.00",
113 reg = <0x0200f310 0x0 0x0 0x0 0x0>;
115 clock-frequency = <58982400>;
116 current-speed = <115200>;
120 reg = <0x0000f800 0 0 0 0>;
121 compatible = "pci8086,0f1c", "intel,pch9";
122 #address-cells = <1>;
126 compatible = "intel,irq-router";
127 intel,pirq-config = "ibase";
128 intel,ibase-offset = <0x50>;
129 intel,actl-addr = <0>;
130 intel,pirq-link = <8 8>;
131 intel,pirq-mask = <0xdee0>;
132 intel,pirq-routing = <
133 /* BayTrail PCI devices */
134 PCI_BDF(0, 2, 0) INTA PIRQA
135 PCI_BDF(0, 3, 0) INTA PIRQA
136 PCI_BDF(0, 16, 0) INTA PIRQA
137 PCI_BDF(0, 17, 0) INTA PIRQA
138 PCI_BDF(0, 18, 0) INTA PIRQA
139 PCI_BDF(0, 19, 0) INTA PIRQA
140 PCI_BDF(0, 20, 0) INTA PIRQA
141 PCI_BDF(0, 21, 0) INTA PIRQA
142 PCI_BDF(0, 22, 0) INTA PIRQA
143 PCI_BDF(0, 23, 0) INTA PIRQA
144 PCI_BDF(0, 24, 0) INTA PIRQA
145 PCI_BDF(0, 24, 1) INTC PIRQC
146 PCI_BDF(0, 24, 2) INTD PIRQD
147 PCI_BDF(0, 24, 3) INTB PIRQB
148 PCI_BDF(0, 24, 4) INTA PIRQA
149 PCI_BDF(0, 24, 5) INTC PIRQC
150 PCI_BDF(0, 24, 6) INTD PIRQD
151 PCI_BDF(0, 24, 7) INTB PIRQB
152 PCI_BDF(0, 26, 0) INTA PIRQA
153 PCI_BDF(0, 27, 0) INTA PIRQA
154 PCI_BDF(0, 28, 0) INTA PIRQA
155 PCI_BDF(0, 28, 1) INTB PIRQB
156 PCI_BDF(0, 28, 2) INTC PIRQC
157 PCI_BDF(0, 28, 3) INTD PIRQD
158 PCI_BDF(0, 29, 0) INTA PIRQA
159 PCI_BDF(0, 30, 0) INTA PIRQA
160 PCI_BDF(0, 30, 1) INTD PIRQD
161 PCI_BDF(0, 30, 2) INTB PIRQB
162 PCI_BDF(0, 30, 3) INTC PIRQC
163 PCI_BDF(0, 30, 4) INTD PIRQD
164 PCI_BDF(0, 30, 5) INTB PIRQB
165 PCI_BDF(0, 31, 3) INTB PIRQB
168 * PCIe root ports downstream
171 PCI_BDF(1, 0, 0) INTA PIRQA
172 PCI_BDF(1, 0, 0) INTB PIRQB
173 PCI_BDF(1, 0, 0) INTC PIRQC
174 PCI_BDF(1, 0, 0) INTD PIRQD
175 PCI_BDF(2, 0, 0) INTA PIRQB
176 PCI_BDF(2, 0, 0) INTB PIRQC
177 PCI_BDF(2, 0, 0) INTC PIRQD
178 PCI_BDF(2, 0, 0) INTD PIRQA
179 PCI_BDF(3, 0, 0) INTA PIRQC
180 PCI_BDF(3, 0, 0) INTB PIRQD
181 PCI_BDF(3, 0, 0) INTC PIRQA
182 PCI_BDF(3, 0, 0) INTD PIRQB
183 PCI_BDF(4, 0, 0) INTA PIRQD
184 PCI_BDF(4, 0, 0) INTB PIRQA
185 PCI_BDF(4, 0, 0) INTC PIRQB
186 PCI_BDF(4, 0, 0) INTD PIRQC
191 #address-cells = <1>;
193 compatible = "intel,ich9-spi";
195 #address-cells = <1>;
198 compatible = "stmicro,n25q064a",
200 memory-map = <0xff800000 0x00800000>;
202 label = "rw-mrc-cache";
203 reg = <0x006f0000 0x00010000>;
209 compatible = "intel,ich6-gpio";
217 compatible = "intel,ich6-gpio";
225 compatible = "intel,ich6-gpio";
233 compatible = "intel,ich6-gpio";
241 compatible = "intel,ich6-gpio";
249 compatible = "intel,ich6-gpio";
259 compatible = "intel,baytrail-fsp";
260 fsp,mrc-init-tseg-size = <MRC_INIT_TSEG_SIZE_1MB>;
261 fsp,mrc-init-mmio-size = <MRC_INIT_MMIO_SIZE_2048MB>;
262 fsp,mrc-init-spd-addr1 = <0xa0>;
263 fsp,mrc-init-spd-addr2 = <0xa2>;
264 fsp,emmc-boot-mode = <EMMC_BOOT_MODE_AUTO>;
271 fsp,sata-mode = <SATA_MODE_AHCI>;
272 #ifdef CONFIG_USB_XHCI_HCD
275 fsp,lpe-mode = <LPE_MODE_PCI>;
276 fsp,lpss-sio-mode = <LPSS_SIO_MODE_PCI>;
288 fsp,igd-dvmt50-pre-alloc = <IGD_DVMT50_PRE_ALLOC_64MB>;
289 fsp,aperture-size = <APERTURE_SIZE_256MB>;
290 fsp,gtt-size = <GTT_SIZE_2MB>;
291 fsp,scc-mode = <SCC_MODE_PCI>;
292 fsp,os-selection = <OS_SELECTION_LINUX>;
293 fsp,emmc45-ddr50-enabled;
294 fsp,emmc45-retune-timer-value = <8>;
296 fsp,enable-memory-down;
297 fsp,memory-down-params {
298 compatible = "intel,baytrail-fsp-mdp";
299 fsp,dram-speed = <DRAM_SPEED_1333MTS>;
300 fsp,dram-type = <DRAM_TYPE_DDR3L>;
302 fsp,dimm-width = <DIMM_WIDTH_X16>;
303 fsp,dimm-density = <DIMM_DENSITY_8GBIT>;
304 fsp,dimm-bus-width = <DIMM_BUS_WIDTH_64BITS>;
305 fsp,dimm-sides = <DIMM_SIDES_1RANKS>;
307 /* These following values might need a re-visit */
309 fsp,dimm-trpt-rcd = <8>;
314 fsp,dimm-tfaw = <22>;
320 #include "microcode/m0130673325.dtsi"
323 #include "microcode/m0130679907.dtsi"