arch/x86/dts/crownbay.dts

   1 /*
   2  * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 /dts-v1/;
   8
   9 #include <dt-bindings/interrupt-router/intel-irq.h>
  10
  11 /include/ "skeleton.dtsi"
  12 /include/ "serial.dtsi"
  13 /include/ "keyboard.dtsi"
  14 /include/ "rtc.dtsi"
  15 /include/ "tsc_timer.dtsi"
  16
  17 / {
  18         model = "Intel Crown Bay";
  19         compatible = "intel,crownbay", "intel,queensbay";
  20
  21         aliases {
  22                 spi0 = &spi;
  23         };
  24
  25         config {
  26                 silent_console = <0>;
  27         };
  28
  29         cpus {
  30                 #address-cells = <1>;
  31                 #size-cells = <0>;
  32
  33                 cpu@0 {
  34                         device_type = "cpu";
  35                         compatible = "cpu-x86";
  36                         reg = <0>;
  37                         intel,apic-id = <0>;
  38                 };
  39
  40                 cpu@1 {
  41                         device_type = "cpu";
  42                         compatible = "cpu-x86";
  43                         reg = <1>;
  44                         intel,apic-id = <1>;
  45                 };
  46
  47         };
  48
  49         chosen {
  50                 /*
  51                  * By default the legacy superio serial port is used as the
  52                  * U-Boot serial console. If we want to use UART from Topcliff
  53                  * PCH as the console, change this property to &pciuart#.
  54                  *
  55                  * For example, stdout-path = &pciuart0 will use the first
  56                  * UART on Topcliff PCH.
  57                  */
  58                 stdout-path = "/serial";
  59         };
  60
  61         microcode {
  62                 update@0 {
  63 #include "microcode/m0220661105_cv.dtsi"
  64                 };
  65         };
  66
  67         pci {
  68                 #address-cells = <3>;
  69                 #size-cells = <2>;
  70                 compatible = "pci-x86";
  71                 u-boot,dm-pre-reloc;
  72                 ranges = <0x02000000 0x0 0x40000000 0x40000000 0 0x80000000
  73                           0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000
  74                           0x01000000 0x0 0x2000 0x2000 0 0xe000>;
  75
  76                 pcie@17,0 {
  77                         #address-cells = <3>;
  78                         #size-cells = <2>;
  79                         compatible = "pci-bridge";
  80                         u-boot,dm-pre-reloc;
  81                         reg = <0x0000b800 0x0 0x0 0x0 0x0>;
  82
  83                         topcliff@0,0 {
  84                                 #address-cells = <3>;
  85                                 #size-cells = <2>;
  86                                 compatible = "pci-bridge";
  87                                 u-boot,dm-pre-reloc;
  88                                 reg = <0x00010000 0x0 0x0 0x0 0x0>;
  89
  90                                 pciuart0: uart@a,1 {
  91                                         compatible = "pci8086,8811.00",
  92                                                         "pci8086,8811",
  93                                                         "pciclass,070002",
  94                                                         "pciclass,0700",
  95                                                         "ns16550";
  96                                         u-boot,dm-pre-reloc;
  97                                         reg = <0x00025100 0x0 0x0 0x0 0x0
  98                                                0x01025110 0x0 0x0 0x0 0x0>;
  99                                         reg-shift = <0>;
 100                                         clock-frequency = <1843200>;
 101                                         current-speed = <115200>;
 102                                 };
 103
 104                                 pciuart1: uart@a,2 {
 105                                         compatible = "pci8086,8812.00",
 106                                                         "pci8086,8812",
 107                                                         "pciclass,070002",
 108                                                         "pciclass,0700",
 109                                                         "ns16550";
 110                                         u-boot,dm-pre-reloc;
 111                                         reg = <0x00025200 0x0 0x0 0x0 0x0
 112                                                0x01025210 0x0 0x0 0x0 0x0>;
 113                                         reg-shift = <0>;
 114                                         clock-frequency = <1843200>;
 115                                         current-speed = <115200>;
 116                                 };
 117
 118                                 pciuart2: uart@a,3 {
 119                                         compatible = "pci8086,8813.00",
 120                                                         "pci8086,8813",
 121                                                         "pciclass,070002",
 122                                                         "pciclass,0700",
 123                                                         "ns16550";
 124                                         u-boot,dm-pre-reloc;
 125                                         reg = <0x00025300 0x0 0x0 0x0 0x0
 126                                                0x01025310 0x0 0x0 0x0 0x0>;
 127                                         reg-shift = <0>;
 128                                         clock-frequency = <1843200>;
 129                                         current-speed = <115200>;
 130                                 };
 131
 132                                 pciuart3: uart@a,4 {
 133                                         compatible = "pci8086,8814.00",
 134                                                         "pci8086,8814",
 135                                                         "pciclass,070002",
 136                                                         "pciclass,0700",
 137                                                         "ns16550";
 138                                         u-boot,dm-pre-reloc;
 139                                         reg = <0x00025400 0x0 0x0 0x0 0x0
 140                                                0x01025410 0x0 0x0 0x0 0x0>;
 141                                         reg-shift = <0>;
 142                                         clock-frequency = <1843200>;
 143                                         current-speed = <115200>;
 144                                 };
 145                         };
 146                 };
 147
 148                 pch@1f,0 {
 149                         reg = <0x0000f800 0 0 0 0>;
 150                         compatible = "intel,pch7";
 151                         #address-cells = <1>;
 152                         #size-cells = <1>;
 153
 154                         irq-router {
 155                                 compatible = "intel,queensbay-irq-router";
 156                                 intel,pirq-config = "pci";
 157                                 intel,pirq-link = <0x60 8>;
 158                                 intel,pirq-mask = <0xcee0>;
 159                                 intel,pirq-routing = <
 160                                         /* TunnelCreek PCI devices */
 161                                         PCI_BDF(0, 2, 0) INTA PIRQE
 162                                         PCI_BDF(0, 3, 0) INTA PIRQF
 163                                         PCI_BDF(0, 23, 0) INTA PIRQA
 164                                         PCI_BDF(0, 23, 0) INTB PIRQB
 165                                         PCI_BDF(0, 23, 0) INTC PIRQC
 166                                         PCI_BDF(0, 23, 0) INTD PIRQD
 167                                         PCI_BDF(0, 24, 0) INTA PIRQB
 168                                         PCI_BDF(0, 24, 0) INTB PIRQC
 169                                         PCI_BDF(0, 24, 0) INTC PIRQD
 170                                         PCI_BDF(0, 24, 0) INTD PIRQA
 171                                         PCI_BDF(0, 25, 0) INTA PIRQC
 172                                         PCI_BDF(0, 25, 0) INTB PIRQD
 173                                         PCI_BDF(0, 25, 0) INTC PIRQA
 174                                         PCI_BDF(0, 25, 0) INTD PIRQB
 175                                         PCI_BDF(0, 26, 0) INTA PIRQD
 176                                         PCI_BDF(0, 26, 0) INTB PIRQA
 177                                         PCI_BDF(0, 26, 0) INTC PIRQB
 178                                         PCI_BDF(0, 26, 0) INTD PIRQC
 179                                         PCI_BDF(0, 27, 0) INTA PIRQG
 180                                         /*
 181                                         * Topcliff PCI devices
 182                                         *
 183                                         * Note on the Crown Bay board, Topcliff
 184                                         * chipset is connected to TunnelCreek
 185                                         * PCIe port 0, so its bus number is 1
 186                                         * for its PCIe port and 2 for its PCI
 187                                         * devices per U-Boot current PCI bus
 188                                         * enumeration algorithm.
 189                                         */
 190                                         PCI_BDF(1, 0, 0) INTA PIRQA
 191                                         PCI_BDF(2, 0, 1) INTA PIRQA
 192                                         PCI_BDF(2, 0, 2) INTA PIRQA
 193                                         PCI_BDF(2, 2, 0) INTB PIRQD
 194                                         PCI_BDF(2, 2, 1) INTB PIRQD
 195                                         PCI_BDF(2, 2, 2) INTB PIRQD
 196                                         PCI_BDF(2, 2, 3) INTB PIRQD
 197                                         PCI_BDF(2, 2, 4) INTB PIRQD
 198                                         PCI_BDF(2, 4, 0) INTC PIRQC
 199                                         PCI_BDF(2, 4, 1) INTC PIRQC
 200                                         PCI_BDF(2, 6, 0) INTD PIRQB
 201                                         PCI_BDF(2, 8, 0) INTA PIRQA
 202                                         PCI_BDF(2, 8, 1) INTA PIRQA
 203                                         PCI_BDF(2, 8, 2) INTA PIRQA
 204                                         PCI_BDF(2, 8, 3) INTA PIRQA
 205                                         PCI_BDF(2, 10, 0) INTB PIRQD
 206                                         PCI_BDF(2, 10, 1) INTB PIRQD
 207                                         PCI_BDF(2, 10, 2) INTB PIRQD
 208                                         PCI_BDF(2, 10, 3) INTB PIRQD
 209                                         PCI_BDF(2, 10, 4) INTB PIRQD
 210                                         PCI_BDF(2, 12, 0) INTC PIRQC
 211                                         PCI_BDF(2, 12, 1) INTC PIRQC
 212                                         PCI_BDF(2, 12, 2) INTC PIRQC
 213                                         PCI_BDF(2, 12, 3) INTC PIRQC
 214                                         PCI_BDF(2, 12, 4) INTC PIRQC
 215                                 >;
 216                         };
 217
 218                         spi: spi {
 219                                 #address-cells = <1>;
 220                                 #size-cells = <0>;
 221                                 compatible = "intel,ich7-spi";
 222                                 spi-flash@0 {
 223                                         reg = <0>;
 224                                         compatible = "sst,25vf016b",
 225                                                 "spi-flash";
 226                                         memory-map = <0xffe00000 0x00200000>;
 227                                 };
 228                         };
 229
 230                         gpioa {
 231                                 compatible = "intel,ich6-gpio";
 232                                 u-boot,dm-pre-reloc;
 233                                 reg = <0 0x20>;
 234                                 bank-name = "A";
 235                         };
 236
 237                         gpiob {
 238                                 compatible = "intel,ich6-gpio";
 239                                 u-boot,dm-pre-reloc;
 240                                 reg = <0x20 0x20>;
 241                                 bank-name = "B";
 242                         };
 243                 };
 244         };
 245
 246 };