arch/x86/dts/crownbay.dts

   1 /*
   2  * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 /dts-v1/;
   8
   9 #include <dt-bindings/interrupt-router/intel-irq.h>
  10
  11 /include/ "skeleton.dtsi"
  12 /include/ "serial.dtsi"
  13 /include/ "keyboard.dtsi"
  14 /include/ "rtc.dtsi"
  15 /include/ "tsc_timer.dtsi"
  16
  17 / {
  18         model = "Intel Crown Bay";
  19         compatible = "intel,crownbay", "intel,queensbay";
  20
  21         aliases {
  22                 spi0 = "/spi";
  23         };
  24
  25         config {
  26                 silent_console = <0>;
  27         };
  28
  29         cpus {
  30                 #address-cells = <1>;
  31                 #size-cells = <0>;
  32
  33                 cpu@0 {
  34                         device_type = "cpu";
  35                         compatible = "cpu-x86";
  36                         reg = <0>;
  37                         intel,apic-id = <0>;
  38                 };
  39
  40                 cpu@1 {
  41                         device_type = "cpu";
  42                         compatible = "cpu-x86";
  43                         reg = <1>;
  44                         intel,apic-id = <1>;
  45                 };
  46
  47         };
  48
  49         gpioa {
  50                 compatible = "intel,ich6-gpio";
  51                 u-boot,dm-pre-reloc;
  52                 reg = <0 0x20>;
  53                 bank-name = "A";
  54         };
  55
  56         gpiob {
  57                 compatible = "intel,ich6-gpio";
  58                 u-boot,dm-pre-reloc;
  59                 reg = <0x20 0x20>;
  60                 bank-name = "B";
  61         };
  62
  63         chosen {
  64                 /*
  65                  * By default the legacy superio serial port is used as the
  66                  * U-Boot serial console. If we want to use UART from Topcliff
  67                  * PCH as the console, change this property to &pciuart#.
  68                  *
  69                  * For example, stdout-path = &pciuart0 will use the first
  70                  * UART on Topcliff PCH.
  71                  */
  72                 stdout-path = "/serial";
  73         };
  74
  75         microcode {
  76                 update@0 {
  77 #include "microcode/m0220661105_cv.dtsi"
  78                 };
  79         };
  80
  81         pci {
  82                 #address-cells = <3>;
  83                 #size-cells = <2>;
  84                 compatible = "pci-x86";
  85                 u-boot,dm-pre-reloc;
  86                 ranges = <0x02000000 0x0 0x40000000 0x40000000 0 0x80000000
  87                           0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000
  88                           0x01000000 0x0 0x2000 0x2000 0 0xe000>;
  89
  90                 pcie@17,0 {
  91                         #address-cells = <3>;
  92                         #size-cells = <2>;
  93                         compatible = "pci-bridge";
  94                         u-boot,dm-pre-reloc;
  95                         reg = <0x0000b800 0x0 0x0 0x0 0x0>;
  96
  97                         topcliff@0,0 {
  98                                 #address-cells = <3>;
  99                                 #size-cells = <2>;
 100                                 compatible = "pci-bridge";
 101                                 u-boot,dm-pre-reloc;
 102                                 reg = <0x00010000 0x0 0x0 0x0 0x0>;
 103
 104                                 pciuart0: uart@a,1 {
 105                                         compatible = "pci8086,8811.00",
 106                                                         "pci8086,8811",
 107                                                         "pciclass,070002",
 108                                                         "pciclass,0700",
 109                                                         "ns16550";
 110                                         u-boot,dm-pre-reloc;
 111                                         reg = <0x00025100 0x0 0x0 0x0 0x0
 112                                                0x01025110 0x0 0x0 0x0 0x0>;
 113                                         reg-shift = <0>;
 114                                         clock-frequency = <1843200>;
 115                                         current-speed = <115200>;
 116                                 };
 117
 118                                 pciuart1: uart@a,2 {
 119                                         compatible = "pci8086,8812.00",
 120                                                         "pci8086,8812",
 121                                                         "pciclass,070002",
 122                                                         "pciclass,0700",
 123                                                         "ns16550";
 124                                         u-boot,dm-pre-reloc;
 125                                         reg = <0x00025200 0x0 0x0 0x0 0x0
 126                                                0x01025210 0x0 0x0 0x0 0x0>;
 127                                         reg-shift = <0>;
 128                                         clock-frequency = <1843200>;
 129                                         current-speed = <115200>;
 130                                 };
 131
 132                                 pciuart2: uart@a,3 {
 133                                         compatible = "pci8086,8813.00",
 134                                                         "pci8086,8813",
 135                                                         "pciclass,070002",
 136                                                         "pciclass,0700",
 137                                                         "ns16550";
 138                                         u-boot,dm-pre-reloc;
 139                                         reg = <0x00025300 0x0 0x0 0x0 0x0
 140                                                0x01025310 0x0 0x0 0x0 0x0>;
 141                                         reg-shift = <0>;
 142                                         clock-frequency = <1843200>;
 143                                         current-speed = <115200>;
 144                                 };
 145
 146                                 pciuart3: uart@a,4 {
 147                                         compatible = "pci8086,8814.00",
 148                                                         "pci8086,8814",
 149                                                         "pciclass,070002",
 150                                                         "pciclass,0700",
 151                                                         "ns16550";
 152                                         u-boot,dm-pre-reloc;
 153                                         reg = <0x00025400 0x0 0x0 0x0 0x0
 154                                                0x01025410 0x0 0x0 0x0 0x0>;
 155                                         reg-shift = <0>;
 156                                         clock-frequency = <1843200>;
 157                                         current-speed = <115200>;
 158                                 };
 159                         };
 160                 };
 161
 162                 pch@1f,0 {
 163                         reg = <0x0000f800 0 0 0 0>;
 164                         compatible = "intel,pch7";
 165
 166                         irq-router {
 167                                 compatible = "intel,queensbay-irq-router";
 168                                 intel,pirq-config = "pci";
 169                                 intel,pirq-link = <0x60 8>;
 170                                 intel,pirq-mask = <0xcee0>;
 171                                 intel,pirq-routing = <
 172                                         /* TunnelCreek PCI devices */
 173                                         PCI_BDF(0, 2, 0) INTA PIRQE
 174                                         PCI_BDF(0, 3, 0) INTA PIRQF
 175                                         PCI_BDF(0, 23, 0) INTA PIRQA
 176                                         PCI_BDF(0, 23, 0) INTB PIRQB
 177                                         PCI_BDF(0, 23, 0) INTC PIRQC
 178                                         PCI_BDF(0, 23, 0) INTD PIRQD
 179                                         PCI_BDF(0, 24, 0) INTA PIRQB
 180                                         PCI_BDF(0, 24, 0) INTB PIRQC
 181                                         PCI_BDF(0, 24, 0) INTC PIRQD
 182                                         PCI_BDF(0, 24, 0) INTD PIRQA
 183                                         PCI_BDF(0, 25, 0) INTA PIRQC
 184                                         PCI_BDF(0, 25, 0) INTB PIRQD
 185                                         PCI_BDF(0, 25, 0) INTC PIRQA
 186                                         PCI_BDF(0, 25, 0) INTD PIRQB
 187                                         PCI_BDF(0, 26, 0) INTA PIRQD
 188                                         PCI_BDF(0, 26, 0) INTB PIRQA
 189                                         PCI_BDF(0, 26, 0) INTC PIRQB
 190                                         PCI_BDF(0, 26, 0) INTD PIRQC
 191                                         PCI_BDF(0, 27, 0) INTA PIRQG
 192                                         /*
 193                                         * Topcliff PCI devices
 194                                         *
 195                                         * Note on the Crown Bay board, Topcliff
 196                                         * chipset is connected to TunnelCreek
 197                                         * PCIe port 0, so its bus number is 1
 198                                         * for its PCIe port and 2 for its PCI
 199                                         * devices per U-Boot current PCI bus
 200                                         * enumeration algorithm.
 201                                         */
 202                                         PCI_BDF(1, 0, 0) INTA PIRQA
 203                                         PCI_BDF(2, 0, 1) INTA PIRQA
 204                                         PCI_BDF(2, 0, 2) INTA PIRQA
 205                                         PCI_BDF(2, 2, 0) INTB PIRQD
 206                                         PCI_BDF(2, 2, 1) INTB PIRQD
 207                                         PCI_BDF(2, 2, 2) INTB PIRQD
 208                                         PCI_BDF(2, 2, 3) INTB PIRQD
 209                                         PCI_BDF(2, 2, 4) INTB PIRQD
 210                                         PCI_BDF(2, 4, 0) INTC PIRQC
 211                                         PCI_BDF(2, 4, 1) INTC PIRQC
 212                                         PCI_BDF(2, 6, 0) INTD PIRQB
 213                                         PCI_BDF(2, 8, 0) INTA PIRQA
 214                                         PCI_BDF(2, 8, 1) INTA PIRQA
 215                                         PCI_BDF(2, 8, 2) INTA PIRQA
 216                                         PCI_BDF(2, 8, 3) INTA PIRQA
 217                                         PCI_BDF(2, 10, 0) INTB PIRQD
 218                                         PCI_BDF(2, 10, 1) INTB PIRQD
 219                                         PCI_BDF(2, 10, 2) INTB PIRQD
 220                                         PCI_BDF(2, 10, 3) INTB PIRQD
 221                                         PCI_BDF(2, 10, 4) INTB PIRQD
 222                                         PCI_BDF(2, 12, 0) INTC PIRQC
 223                                         PCI_BDF(2, 12, 1) INTC PIRQC
 224                                         PCI_BDF(2, 12, 2) INTC PIRQC
 225                                         PCI_BDF(2, 12, 3) INTC PIRQC
 226                                         PCI_BDF(2, 12, 4) INTC PIRQC
 227                                 >;
 228                         };
 229
 230                         spi {
 231                                 #address-cells = <1>;
 232                                 #size-cells = <0>;
 233                                 compatible = "intel,ich-spi";
 234                                 spi-flash@0 {
 235                                         reg = <0>;
 236                                         compatible = "sst,25vf016b",
 237                                                 "spi-flash";
 238                                         memory-map = <0xffe00000 0x00200000>;
 239                                 };
 240                         };
 241                 };
 242         };
 243
 244 };