1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
8 #include <dt-bindings/interrupt-router/intel-irq.h>
10 /include/ "skeleton.dtsi"
11 /include/ "serial.dtsi"
12 /include/ "keyboard.dtsi"
13 /include/ "pcspkr.dtsi"
14 /include/ "reset.dtsi"
16 /include/ "tsc_timer.dtsi"
19 model = "Intel Crown Bay";
20 compatible = "intel,crownbay", "intel,queensbay";
36 compatible = "cpu-x86";
43 compatible = "cpu-x86";
52 * By default the legacy superio serial port is used as the
53 * U-Boot serial console. If we want to use UART from Topcliff
54 * PCH as the console, change this property to &pciuart#.
56 * For example, stdout-path = &pciuart0 will use the first
57 * UART on Topcliff PCH.
59 stdout-path = "/serial";
64 #include "microcode/m0220661105_cv.dtsi"
71 compatible = "pci-x86";
73 ranges = <0x02000000 0x0 0x40000000 0x40000000 0 0x80000000
74 0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000
75 0x01000000 0x0 0x2000 0x2000 0 0xe000>;
80 compatible = "pci-bridge";
82 reg = <0x0000b800 0x0 0x0 0x0 0x0>;
87 compatible = "pci-bridge";
89 reg = <0x00010000 0x0 0x0 0x0 0x0>;
92 compatible = "pci8086,8811.00",
98 reg = <0x00025100 0x0 0x0 0x0 0x0
99 0x01025110 0x0 0x0 0x0 0x0>;
101 clock-frequency = <1843200>;
102 current-speed = <115200>;
106 compatible = "pci8086,8812.00",
112 reg = <0x00025200 0x0 0x0 0x0 0x0
113 0x01025210 0x0 0x0 0x0 0x0>;
115 clock-frequency = <1843200>;
116 current-speed = <115200>;
120 compatible = "pci8086,8813.00",
126 reg = <0x00025300 0x0 0x0 0x0 0x0
127 0x01025310 0x0 0x0 0x0 0x0>;
129 clock-frequency = <1843200>;
130 current-speed = <115200>;
134 compatible = "pci8086,8814.00",
140 reg = <0x00025400 0x0 0x0 0x0 0x0
141 0x01025410 0x0 0x0 0x0 0x0>;
143 clock-frequency = <1843200>;
144 current-speed = <115200>;
150 reg = <0x0000f800 0 0 0 0>;
151 compatible = "intel,pch7";
152 #address-cells = <1>;
156 compatible = "intel,irq-router";
157 intel,pirq-config = "pci";
158 intel,actl-addr = <0x58>;
159 intel,pirq-link = <0x60 8>;
160 intel,pirq-mask = <0xcee0>;
161 intel,pirq-routing = <
162 /* TunnelCreek PCI devices */
163 PCI_BDF(0, 2, 0) INTA PIRQE
164 PCI_BDF(0, 3, 0) INTA PIRQF
165 PCI_BDF(0, 23, 0) INTA PIRQA
166 PCI_BDF(0, 23, 0) INTB PIRQB
167 PCI_BDF(0, 23, 0) INTC PIRQC
168 PCI_BDF(0, 23, 0) INTD PIRQD
169 PCI_BDF(0, 24, 0) INTA PIRQB
170 PCI_BDF(0, 24, 0) INTB PIRQC
171 PCI_BDF(0, 24, 0) INTC PIRQD
172 PCI_BDF(0, 24, 0) INTD PIRQA
173 PCI_BDF(0, 25, 0) INTA PIRQC
174 PCI_BDF(0, 25, 0) INTB PIRQD
175 PCI_BDF(0, 25, 0) INTC PIRQA
176 PCI_BDF(0, 25, 0) INTD PIRQB
177 PCI_BDF(0, 26, 0) INTA PIRQD
178 PCI_BDF(0, 26, 0) INTB PIRQA
179 PCI_BDF(0, 26, 0) INTC PIRQB
180 PCI_BDF(0, 26, 0) INTD PIRQC
181 PCI_BDF(0, 27, 0) INTA PIRQG
183 * Topcliff PCI devices
185 * Note on the Crown Bay board, Topcliff
186 * chipset is connected to TunnelCreek
187 * PCIe port 0, so its bus number is 1
188 * for its PCIe port and 2 for its PCI
189 * devices per U-Boot current PCI bus
190 * enumeration algorithm.
192 PCI_BDF(1, 0, 0) INTA PIRQA
193 PCI_BDF(2, 0, 1) INTA PIRQA
194 PCI_BDF(2, 0, 2) INTA PIRQA
195 PCI_BDF(2, 2, 0) INTB PIRQD
196 PCI_BDF(2, 2, 1) INTB PIRQD
197 PCI_BDF(2, 2, 2) INTB PIRQD
198 PCI_BDF(2, 2, 3) INTB PIRQD
199 PCI_BDF(2, 2, 4) INTB PIRQD
200 PCI_BDF(2, 4, 0) INTC PIRQC
201 PCI_BDF(2, 4, 1) INTC PIRQC
202 PCI_BDF(2, 6, 0) INTD PIRQB
203 PCI_BDF(2, 8, 0) INTA PIRQA
204 PCI_BDF(2, 8, 1) INTA PIRQA
205 PCI_BDF(2, 8, 2) INTA PIRQA
206 PCI_BDF(2, 8, 3) INTA PIRQA
207 PCI_BDF(2, 10, 0) INTB PIRQD
208 PCI_BDF(2, 10, 1) INTB PIRQD
209 PCI_BDF(2, 10, 2) INTB PIRQD
210 PCI_BDF(2, 10, 3) INTB PIRQD
211 PCI_BDF(2, 10, 4) INTB PIRQD
212 PCI_BDF(2, 12, 0) INTC PIRQC
213 PCI_BDF(2, 12, 1) INTC PIRQC
214 PCI_BDF(2, 12, 2) INTC PIRQC
215 PCI_BDF(2, 12, 3) INTC PIRQC
216 PCI_BDF(2, 12, 4) INTC PIRQC
221 #address-cells = <1>;
223 compatible = "intel,ich7-spi";
226 compatible = "sst,25vf016b",
228 memory-map = <0xffe00000 0x00200000>;
233 compatible = "intel,ich6-gpio";
240 compatible = "intel,ich6-gpio";