2 * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
4 * SPDX-License-Identifier: GPL-2.0+
9 #include <dt-bindings/interrupt-router/intel-irq.h>
11 /include/ "skeleton.dtsi"
12 /include/ "serial.dtsi"
16 model = "Intel Crown Bay";
17 compatible = "intel,crownbay", "intel,queensbay";
33 compatible = "cpu-x86";
40 compatible = "cpu-x86";
48 compatible = "intel,ich6-gpio";
55 compatible = "intel,ich6-gpio";
63 * By default the legacy superio serial port is used as the
64 * U-Boot serial console. If we want to use UART from Topcliff
65 * PCH as the console, change this property to &pciuart#.
67 * For example, stdout-path = &pciuart0 will use the first
68 * UART on Topcliff PCH.
70 stdout-path = "/serial";
76 compatible = "intel,ich-spi";
79 compatible = "sst,25vf016b", "spi-flash";
80 memory-map = <0xffe00000 0x00200000>;
86 #include "microcode/m0220661105_cv.dtsi"
93 compatible = "intel,pci";
99 compatible = "intel,pci";
103 #address-cells = <3>;
105 compatible = "intel,pci";
109 compatible = "pci8086,8811.00",
114 reg = <0x00025100 0x0 0x0 0x0 0x0
115 0x01025110 0x0 0x0 0x0 0x0>;
117 clock-frequency = <1843200>;
118 current-speed = <115200>;
122 compatible = "pci8086,8812.00",
127 reg = <0x00025200 0x0 0x0 0x0 0x0
128 0x01025210 0x0 0x0 0x0 0x0>;
130 clock-frequency = <1843200>;
131 current-speed = <115200>;
135 compatible = "pci8086,8813.00",
140 reg = <0x00025300 0x0 0x0 0x0 0x0
141 0x01025310 0x0 0x0 0x0 0x0>;
143 clock-frequency = <1843200>;
144 current-speed = <115200>;
148 compatible = "pci8086,8814.00",
153 reg = <0x00025400 0x0 0x0 0x0 0x0
154 0x01025410 0x0 0x0 0x0 0x0>;
156 clock-frequency = <1843200>;
157 current-speed = <115200>;
163 reg = <0x0000f800 0 0 0 0>;
164 compatible = "intel,irq-router";
165 intel,pirq-config = "pci";
166 intel,pirq-link = <0x60 8>;
167 intel,pirq-mask = <0xdee0>;
168 intel,pirq-routing = <
169 /* TunnelCreek PCI devices */
170 PCI_BDF(0, 2, 0) INTA PIRQE
171 PCI_BDF(0, 3, 0) INTA PIRQF
172 PCI_BDF(0, 23, 0) INTA PIRQE
173 PCI_BDF(0, 24, 0) INTA PIRQF
174 PCI_BDF(0, 25, 0) INTA PIRQG
175 PCI_BDF(0, 26, 0) INTA PIRQH
176 PCI_BDF(0, 27, 0) INTA PIRQG
178 * Topcliff PCI devices
180 * Note on the Crown Bay board, Topcliff chipset
181 * is connected to TunnelCreek PCIe port 0, so
182 * its bus number is 1 for its PCIe port and 2
183 * for its PCI devices per U-Boot currnet PCI
184 * bus enumeration algorithm.
186 PCI_BDF(1, 0, 0) INTA PIRQA
187 PCI_BDF(2, 0, 1) INTA PIRQA
188 PCI_BDF(2, 0, 2) INTA PIRQA
189 PCI_BDF(2, 2, 0) INTB PIRQB
190 PCI_BDF(2, 2, 1) INTB PIRQB
191 PCI_BDF(2, 2, 2) INTB PIRQB
192 PCI_BDF(2, 2, 3) INTB PIRQB
193 PCI_BDF(2, 2, 4) INTB PIRQB
194 PCI_BDF(2, 4, 0) INTC PIRQC
195 PCI_BDF(2, 4, 1) INTC PIRQC
196 PCI_BDF(2, 6, 0) INTD PIRQD
197 PCI_BDF(2, 8, 0) INTA PIRQA
198 PCI_BDF(2, 8, 1) INTA PIRQA
199 PCI_BDF(2, 8, 2) INTA PIRQA
200 PCI_BDF(2, 8, 3) INTA PIRQA
201 PCI_BDF(2, 10, 0) INTB PIRQB
202 PCI_BDF(2, 10, 1) INTB PIRQB
203 PCI_BDF(2, 10, 2) INTB PIRQB
204 PCI_BDF(2, 10, 3) INTB PIRQB
205 PCI_BDF(2, 10, 4) INTB PIRQB
206 PCI_BDF(2, 12, 0) INTC PIRQC
207 PCI_BDF(2, 12, 1) INTC PIRQC
208 PCI_BDF(2, 12, 2) INTC PIRQC
209 PCI_BDF(2, 12, 3) INTC PIRQC
210 PCI_BDF(2, 12, 4) INTC PIRQC