2 * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
4 * SPDX-License-Identifier: GPL-2.0+
9 #include <dt-bindings/interrupt-router/intel-irq.h>
11 /include/ "skeleton.dtsi"
12 /include/ "serial.dtsi"
13 /include/ "keyboard.dtsi"
15 /include/ "tsc_timer.dtsi"
18 model = "Intel Crown Bay";
19 compatible = "intel,crownbay", "intel,queensbay";
35 compatible = "cpu-x86";
42 compatible = "cpu-x86";
50 compatible = "intel,ich6-gpio";
57 compatible = "intel,ich6-gpio";
65 * By default the legacy superio serial port is used as the
66 * U-Boot serial console. If we want to use UART from Topcliff
67 * PCH as the console, change this property to &pciuart#.
69 * For example, stdout-path = &pciuart0 will use the first
70 * UART on Topcliff PCH.
72 stdout-path = "/serial";
78 compatible = "intel,ich-spi";
81 compatible = "sst,25vf016b", "spi-flash";
82 memory-map = <0xffe00000 0x00200000>;
88 #include "microcode/m0220661105_cv.dtsi"
95 compatible = "pci-x86";
97 ranges = <0x02000000 0x0 0x40000000 0x40000000 0 0x80000000
98 0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000
99 0x01000000 0x0 0x2000 0x2000 0 0xe000>;
102 #address-cells = <3>;
104 compatible = "pci-bridge";
106 reg = <0x0000b800 0x0 0x0 0x0 0x0>;
109 #address-cells = <3>;
111 compatible = "pci-bridge";
113 reg = <0x00010000 0x0 0x0 0x0 0x0>;
116 compatible = "pci8086,8811.00",
122 reg = <0x00025100 0x0 0x0 0x0 0x0
123 0x01025110 0x0 0x0 0x0 0x0>;
125 clock-frequency = <1843200>;
126 current-speed = <115200>;
130 compatible = "pci8086,8812.00",
136 reg = <0x00025200 0x0 0x0 0x0 0x0
137 0x01025210 0x0 0x0 0x0 0x0>;
139 clock-frequency = <1843200>;
140 current-speed = <115200>;
144 compatible = "pci8086,8813.00",
150 reg = <0x00025300 0x0 0x0 0x0 0x0
151 0x01025310 0x0 0x0 0x0 0x0>;
153 clock-frequency = <1843200>;
154 current-speed = <115200>;
158 compatible = "pci8086,8814.00",
164 reg = <0x00025400 0x0 0x0 0x0 0x0
165 0x01025410 0x0 0x0 0x0 0x0>;
167 clock-frequency = <1843200>;
168 current-speed = <115200>;
174 reg = <0x0000f800 0 0 0 0>;
175 compatible = "intel,irq-router";
176 intel,pirq-config = "pci";
177 intel,pirq-link = <0x60 8>;
178 intel,pirq-mask = <0xcee0>;
179 intel,pirq-routing = <
180 /* TunnelCreek PCI devices */
181 PCI_BDF(0, 2, 0) INTA PIRQE
182 PCI_BDF(0, 3, 0) INTA PIRQF
183 PCI_BDF(0, 23, 0) INTA PIRQA
184 PCI_BDF(0, 23, 0) INTB PIRQB
185 PCI_BDF(0, 23, 0) INTC PIRQC
186 PCI_BDF(0, 23, 0) INTD PIRQD
187 PCI_BDF(0, 24, 0) INTA PIRQB
188 PCI_BDF(0, 24, 0) INTB PIRQC
189 PCI_BDF(0, 24, 0) INTC PIRQD
190 PCI_BDF(0, 24, 0) INTD PIRQA
191 PCI_BDF(0, 25, 0) INTA PIRQC
192 PCI_BDF(0, 25, 0) INTB PIRQD
193 PCI_BDF(0, 25, 0) INTC PIRQA
194 PCI_BDF(0, 25, 0) INTD PIRQB
195 PCI_BDF(0, 26, 0) INTA PIRQD
196 PCI_BDF(0, 26, 0) INTB PIRQA
197 PCI_BDF(0, 26, 0) INTC PIRQB
198 PCI_BDF(0, 26, 0) INTD PIRQC
199 PCI_BDF(0, 27, 0) INTA PIRQG
201 * Topcliff PCI devices
203 * Note on the Crown Bay board, Topcliff chipset
204 * is connected to TunnelCreek PCIe port 0, so
205 * its bus number is 1 for its PCIe port and 2
206 * for its PCI devices per U-Boot current PCI
207 * bus enumeration algorithm.
209 PCI_BDF(1, 0, 0) INTA PIRQA
210 PCI_BDF(2, 0, 1) INTA PIRQA
211 PCI_BDF(2, 0, 2) INTA PIRQA
212 PCI_BDF(2, 2, 0) INTB PIRQD
213 PCI_BDF(2, 2, 1) INTB PIRQD
214 PCI_BDF(2, 2, 2) INTB PIRQD
215 PCI_BDF(2, 2, 3) INTB PIRQD
216 PCI_BDF(2, 2, 4) INTB PIRQD
217 PCI_BDF(2, 4, 0) INTC PIRQC
218 PCI_BDF(2, 4, 1) INTC PIRQC
219 PCI_BDF(2, 6, 0) INTD PIRQB
220 PCI_BDF(2, 8, 0) INTA PIRQA
221 PCI_BDF(2, 8, 1) INTA PIRQA
222 PCI_BDF(2, 8, 2) INTA PIRQA
223 PCI_BDF(2, 8, 3) INTA PIRQA
224 PCI_BDF(2, 10, 0) INTB PIRQD
225 PCI_BDF(2, 10, 1) INTB PIRQD
226 PCI_BDF(2, 10, 2) INTB PIRQD
227 PCI_BDF(2, 10, 3) INTB PIRQD
228 PCI_BDF(2, 10, 4) INTB PIRQD
229 PCI_BDF(2, 12, 0) INTC PIRQC
230 PCI_BDF(2, 12, 1) INTC PIRQC
231 PCI_BDF(2, 12, 2) INTC PIRQC
232 PCI_BDF(2, 12, 3) INTC PIRQC
233 PCI_BDF(2, 12, 4) INTC PIRQC