arch/x86/dts/cougarcanyon2.dts

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
   4  */
   5
   6 /dts-v1/;
   7
   8 #include <dt-bindings/interrupt-router/intel-irq.h>
   9
  10 /include/ "skeleton.dtsi"
  11 /include/ "serial.dtsi"
  12 /include/ "keyboard.dtsi"
  13 /include/ "reset.dtsi"
  14 /include/ "rtc.dtsi"
  15 /include/ "tsc_timer.dtsi"
  16
  17 / {
  18         model = "Intel Cougar Canyon 2";
  19         compatible = "intel,cougarcanyon2", "intel,chiefriver";
  20
  21         aliases {
  22                 spi0 = &spi0;
  23         };
  24
  25         config {
  26                 silent_console = <0>;
  27         };
  28
  29         chosen {
  30                 stdout-path = "/serial";
  31         };
  32
  33         cpus {
  34                 #address-cells = <1>;
  35                 #size-cells = <0>;
  36
  37                 cpu@0 {
  38                         device_type = "cpu";
  39                         compatible = "intel,core-gen3";
  40                         reg = <0>;
  41                         intel,apic-id = <0>;
  42                 };
  43
  44                 cpu@1 {
  45                         device_type = "cpu";
  46                         compatible = "intel,core-gen3";
  47                         reg = <1>;
  48                         intel,apic-id = <1>;
  49                 };
  50
  51                 cpu@2 {
  52                         device_type = "cpu";
  53                         compatible = "intel,core-gen3";
  54                         reg = <2>;
  55                         intel,apic-id = <2>;
  56                 };
  57
  58                 cpu@3 {
  59                         device_type = "cpu";
  60                         compatible = "intel,core-gen3";
  61                         reg = <3>;
  62                         intel,apic-id = <3>;
  63                 };
  64         };
  65
  66         microcode {
  67                 update@0 {
  68 #include "microcode/m12306a2_00000008.dtsi"
  69                 };
  70                 update@1 {
  71 #include "microcode/m12306a4_00000007.dtsi"
  72                 };
  73                 update@2 {
  74 #include "microcode/m12306a5_00000007.dtsi"
  75                 };
  76                 update@3 {
  77 #include "microcode/m12306a8_00000010.dtsi"
  78                 };
  79                 update@4 {
  80 #include "microcode/m12306a9_0000001b.dtsi"
  81                 };
  82         };
  83
  84         fsp {
  85                 compatible = "intel,ivybridge-fsp";
  86                 fsp,enable-ht;
  87         };
  88
  89         pci {
  90                 #address-cells = <3>;
  91                 #size-cells = <2>;
  92                 compatible = "pci-x86";
  93                 u-boot,dm-pre-reloc;
  94                 ranges = <0x02000000 0x0 0xc0000000 0xc0000000 0 0x10000000
  95                           0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000
  96                           0x01000000 0x0 0x2000 0x2000 0 0xe000>;
  97
  98                 pch@1f,0 {
  99                         reg = <0x0000f800 0 0 0 0>;
 100                         compatible = "intel,bd82x6x";
 101                         u-boot,dm-pre-reloc;
 102                         #address-cells = <1>;
 103                         #size-cells = <1>;
 104
 105                         irq-router {
 106                                 compatible = "intel,irq-router";
 107                                 intel,pirq-config = "pci";
 108                                 intel,actl-8bit;
 109                                 intel,actl-addr = <0x44>;
 110                                 intel,pirq-link = <0x60 8>;
 111                                 intel,pirq-regmap = <
 112                                         PIRQA 0
 113                                         PIRQB 1
 114                                         PIRQC 2
 115                                         PIRQD 3
 116                                         PIRQE 8
 117                                         PIRQF 9
 118                                         PIRQG 10
 119                                         PIRQH 11
 120                                 >;
 121                                 intel,pirq-mask = <0xcee0>;
 122                                 intel,pirq-routing = <
 123                                         /* Panther Point PCI devices */
 124                                         PCI_BDF(0, 2, 0) INTA PIRQA
 125                                         PCI_BDF(0, 20, 0) INTA PIRQA
 126                                         PCI_BDF(0, 22, 0) INTA PIRQA
 127                                         PCI_BDF(0, 22, 1) INTB PIRQB
 128                                         PCI_BDF(0, 22, 2) INTC PIRQC
 129                                         PCI_BDF(0, 22, 3) INTD PIRQD
 130                                         PCI_BDF(0, 25, 0) INTA PIRQA
 131                                         PCI_BDF(0, 26, 0) INTA PIRQA
 132                                         PCI_BDF(0, 27, 0) INTB PIRQA
 133                                         PCI_BDF(0, 28, 0) INTA PIRQA
 134                                         PCI_BDF(0, 28, 1) INTB PIRQB
 135                                         PCI_BDF(0, 28, 2) INTC PIRQC
 136                                         PCI_BDF(0, 28, 3) INTD PIRQD
 137                                         PCI_BDF(0, 28, 4) INTA PIRQA
 138                                         PCI_BDF(0, 28, 5) INTB PIRQB
 139                                         PCI_BDF(0, 28, 6) INTC PIRQC
 140                                         PCI_BDF(0, 28, 7) INTD PIRQD
 141                                         PCI_BDF(0, 29, 0) INTA PIRQA
 142                                         PCI_BDF(0, 31, 2) INTB PIRQB
 143                                         PCI_BDF(0, 31, 3) INTC PIRQC
 144                                         PCI_BDF(0, 31, 5) INTB PIRQB
 145                                         PCI_BDF(0, 31, 6) INTC PIRQC
 146                                 >;
 147                         };
 148
 149                         spi0: spi {
 150                                 #address-cells = <1>;
 151                                 #size-cells = <0>;
 152                                 compatible = "intel,ich9-spi";
 153                                 intel,spi-lock-down;
 154
 155                                 spi-flash@0 {
 156                                         reg = <0>;
 157                                         compatible = "winbond,w25q64bv", "jedec,spi-nor";
 158                                         memory-map = <0xff800000 0x00800000>;
 159                                 };
 160                         };
 161
 162                         gpioa {
 163                                 compatible = "intel,ich6-gpio";
 164                                 u-boot,dm-pre-reloc;
 165                                 reg = <0 0x10>;
 166                                 bank-name = "A";
 167                         };
 168
 169                         gpiob {
 170                                 compatible = "intel,ich6-gpio";
 171                                 u-boot,dm-pre-reloc;
 172                                 reg = <0x30 0x10>;
 173                                 bank-name = "B";
 174                         };
 175
 176                         gpioc {
 177                                 compatible = "intel,ich6-gpio";
 178                                 u-boot,dm-pre-reloc;
 179                                 reg = <0x40 0x10>;
 180                                 bank-name = "C";
 181                         };
 182                 };
 183         };
 184
 185 };