2 * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
3 * Copyright (C) 2016 Stefan Roese <sr@denx.de>
5 * SPDX-License-Identifier: GPL-2.0+
10 #include <dt-bindings/gpio/x86-gpio.h>
11 #include <dt-bindings/interrupt-router/intel-irq.h>
13 /include/ "skeleton.dtsi"
14 /include/ "serial.dtsi"
16 /include/ "tsc_timer.dtsi"
19 model = "congatec-QEVAL20-QA3-E3845";
20 compatible = "congatec,qeval20-qa3-e3845", "intel,baytrail";
32 compatible = "intel,x86-pinctrl";
36 * As of today, the latest version FSP (gold4) for BayTrail
37 * misses the PAD configuration of the SD controller's Card
38 * Detect signal. The default PAD value for the CD pin sets
39 * the pin to work in GPIO mode, which causes card detect
40 * status cannot be reflected by the Present State register
41 * in the SD controller (bit 16 & bit 18 are always zero).
43 * Configure this pin to function 1 (SD controller).
50 /* Add SMBus PAD configuration */
63 stdout-path = "/serial";
72 compatible = "intel,baytrail-cpu";
79 compatible = "intel,baytrail-cpu";
86 compatible = "intel,baytrail-cpu";
93 compatible = "intel,baytrail-cpu";
100 compatible = "intel,pci-baytrail", "pci-x86";
101 #address-cells = <3>;
104 ranges = <0x02000000 0x0 0x80000000 0x80000000 0 0x40000000
105 0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000
106 0x01000000 0x0 0x2000 0x2000 0 0xe000>;
109 reg = <0x0000f800 0 0 0 0>;
110 compatible = "pci8086,0f1c", "intel,pch9";
111 #address-cells = <1>;
115 compatible = "intel,irq-router";
116 intel,pirq-config = "ibase";
117 intel,ibase-offset = <0x50>;
118 intel,actl-addr = <0>;
119 intel,pirq-link = <8 8>;
120 intel,pirq-mask = <0xdee0>;
121 intel,pirq-routing = <
122 /* BayTrail PCI devices */
123 PCI_BDF(0, 2, 0) INTA PIRQA
124 PCI_BDF(0, 3, 0) INTA PIRQA
125 PCI_BDF(0, 16, 0) INTA PIRQA
126 PCI_BDF(0, 17, 0) INTA PIRQA
127 PCI_BDF(0, 18, 0) INTA PIRQA
128 PCI_BDF(0, 19, 0) INTA PIRQA
129 PCI_BDF(0, 20, 0) INTA PIRQA
130 PCI_BDF(0, 21, 0) INTA PIRQA
131 PCI_BDF(0, 22, 0) INTA PIRQA
132 PCI_BDF(0, 23, 0) INTA PIRQA
133 PCI_BDF(0, 24, 0) INTA PIRQA
134 PCI_BDF(0, 24, 1) INTC PIRQC
135 PCI_BDF(0, 24, 2) INTD PIRQD
136 PCI_BDF(0, 24, 3) INTB PIRQB
137 PCI_BDF(0, 24, 4) INTA PIRQA
138 PCI_BDF(0, 24, 5) INTC PIRQC
139 PCI_BDF(0, 24, 6) INTD PIRQD
140 PCI_BDF(0, 24, 7) INTB PIRQB
141 PCI_BDF(0, 26, 0) INTA PIRQA
142 PCI_BDF(0, 27, 0) INTA PIRQA
143 PCI_BDF(0, 28, 0) INTA PIRQA
144 PCI_BDF(0, 28, 1) INTB PIRQB
145 PCI_BDF(0, 28, 2) INTC PIRQC
146 PCI_BDF(0, 28, 3) INTD PIRQD
147 PCI_BDF(0, 29, 0) INTA PIRQA
148 PCI_BDF(0, 30, 0) INTA PIRQA
149 PCI_BDF(0, 30, 1) INTD PIRQD
150 PCI_BDF(0, 30, 2) INTB PIRQB
151 PCI_BDF(0, 30, 3) INTC PIRQC
152 PCI_BDF(0, 30, 4) INTD PIRQD
153 PCI_BDF(0, 30, 5) INTB PIRQB
154 PCI_BDF(0, 31, 3) INTB PIRQB
157 * PCIe root ports downstream
160 PCI_BDF(1, 0, 0) INTA PIRQA
161 PCI_BDF(1, 0, 0) INTB PIRQB
162 PCI_BDF(1, 0, 0) INTC PIRQC
163 PCI_BDF(1, 0, 0) INTD PIRQD
164 PCI_BDF(2, 0, 0) INTA PIRQB
165 PCI_BDF(2, 0, 0) INTB PIRQC
166 PCI_BDF(2, 0, 0) INTC PIRQD
167 PCI_BDF(2, 0, 0) INTD PIRQA
168 PCI_BDF(3, 0, 0) INTA PIRQC
169 PCI_BDF(3, 0, 0) INTB PIRQD
170 PCI_BDF(3, 0, 0) INTC PIRQA
171 PCI_BDF(3, 0, 0) INTD PIRQB
172 PCI_BDF(4, 0, 0) INTA PIRQD
173 PCI_BDF(4, 0, 0) INTB PIRQA
174 PCI_BDF(4, 0, 0) INTC PIRQB
175 PCI_BDF(4, 0, 0) INTD PIRQC
180 #address-cells = <1>;
182 compatible = "intel,ich9-spi";
184 #address-cells = <1>;
187 compatible = "stmicro,n25q064a",
189 memory-map = <0xff800000 0x00800000>;
191 label = "rw-mrc-cache";
192 reg = <0x006f0000 0x00010000>;
198 compatible = "intel,ich6-gpio";
205 compatible = "intel,ich6-gpio";
212 compatible = "intel,ich6-gpio";
219 compatible = "intel,ich6-gpio";
226 compatible = "intel,ich6-gpio";
233 compatible = "intel,ich6-gpio";
242 compatible = "intel,baytrail-fsp";
243 fsp,mrc-init-tseg-size = <0>;
244 fsp,mrc-init-mmio-size = <0x800>;
245 fsp,mrc-init-spd-addr1 = <0xa0>;
246 fsp,mrc-init-spd-addr2 = <0xa2>;
247 fsp,emmc-boot-mode = <1>;
255 fsp,lpss-sio-enable-pci-mode;
260 fsp,igd-dvmt50-pre-alloc = <2>;
261 fsp,aperture-size = <2>;
263 fsp,scc-enable-pci-mode;
264 fsp,os-selection = <4>;
265 fsp,emmc45-ddr50-enabled;
266 fsp,emmc45-retune-timer-value = <8>;
268 fsp,enable-memory-down;
269 fsp,memory-down-params {
270 compatible = "intel,baytrail-fsp-mdp";
271 fsp,dram-speed = <2>; /* 2=1333MHz */
272 fsp,dram-type = <1>; /* 1=DDR3L */
275 fsp,dimm-width = <1>; /* 1=x16, 2=x32 */
276 fsp,dimm-density = <2>; /* 2=4Gbit */
277 fsp,dimm-bus-width = <3>; /* 3=64bits */
278 fsp,dimm-sides = <0>; /* 0=1 ranks -> 0x2b */
280 /* These following values might need a re-visit */
282 fsp,dimm-trpt-rcd = <8>;
287 fsp,dimm-tfaw = <22>;
293 #include "microcode/m0130673325.dtsi"
296 #include "microcode/m0130679907.dtsi"