arch/x86/dts/chromebox_panther.dts

   1 /dts-v1/;
   2
   3 /include/ "skeleton.dtsi"
   4 /include/ "serial.dtsi"
   5 /include/ "reset.dtsi"
   6 /include/ "rtc.dtsi"
   7 /include/ "tsc_timer.dtsi"
   8
   9 / {
  10         model = "Google Panther";
  11         compatible = "google,panther", "intel,haswell";
  12
  13         aliases {
  14                 spi0 = &spi;
  15         };
  16
  17         config {
  18                 silent-console = <0>;
  19                 no-keyboard;
  20         };
  21
  22         chosen {
  23                 stdout-path = "/serial";
  24         };
  25
  26         pci {
  27                 compatible = "pci-x86";
  28                 #address-cells = <3>;
  29                 #size-cells = <2>;
  30                 u-boot,dm-pre-reloc;
  31                 ranges = <0x02000000 0x0 0xe0000000 0xe0000000 0 0x10000000
  32                         0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000
  33                         0x01000000 0x0 0x1000 0x1000 0 0xf000>;
  34
  35                 pch@1f,0 {
  36                         reg = <0x0000f800 0 0 0 0>;
  37                         compatible = "intel,pch9";
  38                         #address-cells = <1>;
  39                         #size-cells = <1>;
  40
  41                         spi: spi {
  42                                 #address-cells = <1>;
  43                                 #size-cells = <0>;
  44                                 compatible = "intel,ich9-spi";
  45                                 spi-flash@0 {
  46                                         #size-cells = <1>;
  47                                         #address-cells = <1>;
  48                                         reg = <0>;
  49                                         compatible = "winbond,w25q64",
  50                                                 "spi-flash";
  51                                         memory-map = <0xff800000 0x00800000>;
  52                                         rw-mrc-cache {
  53                                                 label = "rw-mrc-cache";
  54                                                 reg = <0x003e0000 0x00010000>;
  55                                         };
  56                                 };
  57                         };
  58
  59                         gpioa {
  60                                 compatible = "intel,ich6-gpio";
  61                                 u-boot,dm-pre-reloc;
  62                                 reg = <0 0x10>;
  63                                 bank-name = "A";
  64                         };
  65
  66                         gpiob {
  67                                 compatible = "intel,ich6-gpio";
  68                                 u-boot,dm-pre-reloc;
  69                                 reg = <0x30 0x10>;
  70                                 bank-name = "B";
  71                         };
  72
  73                         gpioc {
  74                                 compatible = "intel,ich6-gpio";
  75                                 u-boot,dm-pre-reloc;
  76                                 reg = <0x40 0x10>;
  77                                 bank-name = "C";
  78                         };
  79                 };
  80         };
  81
  82         tpm {
  83                 reg = <0xfed40000 0x5000>;
  84                 compatible = "infineon,slb9635lpc";
  85         };
  86
  87 };