arch/x86/dts/chromebox_panther.dts

   1 /dts-v1/;
   2
   3 /include/ "skeleton.dtsi"
   4 /include/ "serial.dtsi"
   5 /include/ "reset.dtsi"
   6 /include/ "rtc.dtsi"
   7 /include/ "tsc_timer.dtsi"
   8 /include/ "coreboot_fb.dtsi"
   9
  10 / {
  11         model = "Google Panther";
  12         compatible = "google,panther", "intel,haswell";
  13
  14         aliases {
  15                 spi0 = &spi;
  16         };
  17
  18         config {
  19                 silent-console = <0>;
  20                 no-keyboard;
  21         };
  22
  23         chosen {
  24                 stdout-path = "/serial";
  25         };
  26
  27         pci {
  28                 compatible = "pci-x86";
  29                 #address-cells = <3>;
  30                 #size-cells = <2>;
  31                 u-boot,dm-pre-reloc;
  32                 ranges = <0x02000000 0x0 0xe0000000 0xe0000000 0 0x10000000
  33                         0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000
  34                         0x01000000 0x0 0x1000 0x1000 0 0xf000>;
  35
  36                 pch@1f,0 {
  37                         reg = <0x0000f800 0 0 0 0>;
  38                         compatible = "intel,pch9";
  39                         #address-cells = <1>;
  40                         #size-cells = <1>;
  41
  42                         spi: spi {
  43                                 #address-cells = <1>;
  44                                 #size-cells = <0>;
  45                                 compatible = "intel,ich9-spi";
  46                                 spi-flash@0 {
  47                                         #size-cells = <1>;
  48                                         #address-cells = <1>;
  49                                         reg = <0>;
  50                                         compatible = "winbond,w25q64",
  51                                                 "spi-flash";
  52                                         memory-map = <0xff800000 0x00800000>;
  53                                         rw-mrc-cache {
  54                                                 label = "rw-mrc-cache";
  55                                                 reg = <0x003e0000 0x00010000>;
  56                                         };
  57                                 };
  58                         };
  59
  60                         gpioa {
  61                                 compatible = "intel,ich6-gpio";
  62                                 u-boot,dm-pre-reloc;
  63                                 reg = <0 0x10>;
  64                                 bank-name = "A";
  65                         };
  66
  67                         gpiob {
  68                                 compatible = "intel,ich6-gpio";
  69                                 u-boot,dm-pre-reloc;
  70                                 reg = <0x30 0x10>;
  71                                 bank-name = "B";
  72                         };
  73
  74                         gpioc {
  75                                 compatible = "intel,ich6-gpio";
  76                                 u-boot,dm-pre-reloc;
  77                                 reg = <0x40 0x10>;
  78                                 bank-name = "C";
  79                         };
  80                 };
  81         };
  82
  83         tpm {
  84                 reg = <0xfed40000 0x5000>;
  85                 compatible = "infineon,slb9635lpc";
  86         };
  87
  88 };