1 /* SPDX-License-Identifier: GPL-2.0 */
4 #include <dt-bindings/gpio/x86-gpio.h>
6 /include/ "skeleton.dtsi"
7 /include/ "keyboard.dtsi"
10 /include/ "tsc_timer.dtsi"
12 #ifdef CONFIG_CHROMEOS
13 #include "chromeos-x86.dtsi"
14 #include "flashmap-x86-ro.dtsi"
15 #include "flashmap-16mb-rw.dtsi"
18 #include <asm/intel_pinctrl_defs.h>
19 #include <asm/arch-apollolake/cpu.h>
20 #include <asm/arch-apollolake/gpio.h>
21 #include <asm/arch-apollolake/iomap.h>
22 #include <asm/arch-apollolake/pm.h>
23 #include <dt-bindings/clock/intel-clock.h>
24 #include <asm/arch-apollolake/fsp/fsp_m_upd.h>
25 #include <asm/arch-apollolake/fsp/fsp_s_upd.h>
28 model = "Google Coral";
29 compatible = "google,coral", "intel,apollolake";
50 stdout-path = &serial;
54 compatible = "intel,apl-clk";
66 compatible = "intel,apl-cpu";
73 compatible = "intel,apl-cpu";
80 compatible = "intel,apl-cpu";
87 compatible = "intel,apl-cpu";
94 acpi_gpe: general-purpose-events {
95 reg = <IOMAP_ACPI_BASE IOMAP_ACPI_SIZE>;
96 compatible = "intel,acpi-gpe";
98 #interrupt-cells = <2>;
106 compatible = "pci-x86";
107 #address-cells = <3>;
110 ranges = <0x02000000 0x0 0xc0000000 0xc0000000 0 0x10000000
111 0x42000000 0x0 0xb0000000 0xb0000000 0 0x10000000
112 0x01000000 0x0 0x1000 0x1000 0 0xefff>;
113 u-boot,skip-auto-config-until-reloc;
115 host_bridge: host-bridge@0,0 {
117 reg = <0x00000000 0 0 0 0>;
118 compatible = "intel,apl-hostbridge";
119 pciex-region-size = <0x10000000>;
121 * Parameters used by the FSP-S binary blob. This is
122 * really unfortunate since these parameters mostly
123 * relate to drivers but we need them in one place. We
124 * could put them in the driver nodes easily, but then
125 * would have to scan each node to find them. So just
126 * dump them here for now.
134 reg = <0x00000800 0 0 0 0>;
135 compatible = "intel,apl-punit";
140 reg = <0x02006810 0 0 0 0>;
141 compatible = "intel,p2sb";
142 early-regs = <IOMAP_P2SB_BAR 0x100000>;
145 compatible = "intel,apl-pinctrl";
147 intel,p2sb-port-id = <PID_GPIO_N>;
149 compatible = "intel,gpio";
158 compatible = "intel,apl-pinctrl";
159 intel,p2sb-port-id = <PID_GPIO_NW>;
162 compatible = "intel,gpio";
171 compatible = "intel,apl-pinctrl";
172 intel,p2sb-port-id = <PID_GPIO_W>;
175 compatible = "intel,gpio";
184 compatible = "intel,apl-pinctrl";
185 intel,p2sb-port-id = <PID_GPIO_SW>;
188 compatible = "intel,gpio";
197 compatible = "intel,itss";
198 intel,p2sb-port-id = <PID_ITSS>;
200 PMC_GPE_SW_31_0 GPIO_GPE_SW_31_0
201 PMC_GPE_SW_63_32 GPIO_GPE_SW_63_32
202 PMC_GPE_NW_31_0 GPIO_GPE_NW_31_0
203 PMC_GPE_NW_63_32 GPIO_GPE_NW_63_32
204 PMC_GPE_NW_95_64 GPIO_GPE_NW_95_64
205 PMC_GPE_N_31_0 GPIO_GPE_N_31_0
206 PMC_GPE_N_63_32 GPIO_GPE_N_63_32
207 PMC_GPE_W_31_0 GPIO_GPE_W_31_0>;
213 reg = <0x6900 0 0 0 0>;
216 * Values for BAR0, BAR2 and ACPI_BASE for when PCI
217 * auto-configure is not available
219 early-regs = <0xfe042000 0x2000
221 IOMAP_ACPI_BASE IOMAP_ACPI_SIZE>;
222 compatible = "intel,apl-pmc";
223 gpe0-dwx-mask = <0xf>;
224 gpe0-dwx-shift-base = <4>;
228 * Note that GPE events called out in ASL code rely on
229 * this route, i.e., if this route changes then the
230 * affected GPE * offset bits also need to be changed.
231 * This sets the PMC register GPE_CFG fields.
233 gpe0-dw = <PMC_GPE_N_31_0
242 reg = <0x02006a10 0 0 0 0>;
243 #address-cells = <1>;
245 compatible = "intel,fast-spi";
246 early-regs = <IOMAP_SPI_BASE 0x1000>;
247 intel,hardware-seq = <1>;
249 fwstore_spi: spi-flash@0 {
251 #address-cells = <1>;
254 compatible = "winbond,w25q128fw",
257 label = "rw-mrc-cache";
258 reg = <0x008e0000 0x00010000>;
262 label = "rw-mrc-cache";
263 reg = <0x008f0000 0x0001000>;
270 compatible = "intel,apl-i2c";
271 reg = <0x0200b010 0 0 0 0>;
272 clocks = <&clk CLK_I2C>;
273 i2c-scl-rising-time-ns = <104>;
274 i2c-scl-falling-time-ns = <52>;
278 compatible = "intel,apl-i2c";
279 reg = <0x0200b110 0 0 0 0>;
280 clocks = <&clk CLK_I2C>;
285 compatible = "intel,apl-i2c";
286 reg = <0x0200b210 0 0 0 0>;
287 #address-cells = <1>;
289 clock-frequency = <400000>;
290 clocks = <&clk CLK_I2C>;
291 i2c-scl-rising-time-ns = <57>;
292 i2c-scl-falling-time-ns = <28>;
295 compatible = "google,cr50";
296 u-boot,i2c-offset-len = <0>;
297 ready-gpios = <&gpio_n 28 GPIO_ACTIVE_LOW>;
298 interrupts-extended = <&acpi_gpe 0x3c 0>;
303 compatible = "intel,apl-i2c";
304 reg = <0x0200b110 0 0 0 0>;
305 clocks = <&clk CLK_I2C>;
306 i2c-scl-rising-time-ns = <76>;
307 i2c-scl-falling-time-ns = <164>;
311 compatible = "intel,apl-i2c";
312 reg = <0x0200b110 0 0 0 0>;
313 clocks = <&clk CLK_I2C>;
314 i2c-sda-hold-time-ns = <350>;
315 i2c-scl-rising-time-ns = <114>;
316 i2c-scl-falling-time-ns = <164>;
320 compatible = "intel,apl-i2c";
321 reg = <0x0200b110 0 0 0 0>;
322 clocks = <&clk CLK_I2C>;
323 i2c-scl-rising-time-ns = <76>;
324 i2c-scl-falling-time-ns = <164>;
328 compatible = "intel,apl-i2c";
329 reg = <0x0200b110 0 0 0 0>;
330 clocks = <&clk CLK_I2C>;
335 compatible = "intel,apl-i2c";
336 reg = <0x0200b110 0 0 0 0>;
337 clocks = <&clk CLK_I2C>;
341 serial: serial@18,2 {
342 reg = <0x0200c210 0 0 0 0>;
344 compatible = "intel,apl-ns16550";
345 early-regs = <0xde000000 0x20>;
347 clock-frequency = <1843200>;
348 current-speed = <115200>;
352 reg = <0x0000f800 0 0 0 0>;
353 compatible = "intel,apl-pch";
355 #address-cells = <1>;
359 compatible = "intel,apl-lpc";
360 #address-cells = <1>;
365 compatible = "google,cros-ec-lpc";
366 reg = <0x204 1 0x200 1 0x880 0x80>;
369 * Describes the flash memory within
372 #address-cells = <1>;
375 reg = <0x08000000 0x20000>;
376 erase-value = <0xff>;
387 * PL1 override 12000 mW: the energy calculation is wrong with the
388 * current VR solution. Experiments show that SoC TDP max (6W) can be
389 * reached when RAPL PL1 is set to 12W. Set RAPL PL2 to 15W.
391 tdp-pl-override-mw = <12000 15000>;
394 /* These two are for the debug UART */
395 GPIO_46 /* UART2 RX */
396 (PAD_CFG0_MODE_NF1 | PAD_CFG0_LOGICAL_RESET_DEEP)
397 (PAD_CFG1_PULL_NATIVE | PAD_CFG1_IOSSTATE_TX_LAST_RXE)
399 GPIO_47 /* UART2 TX */
400 (PAD_CFG0_MODE_NF1 | PAD_CFG0_LOGICAL_RESET_DEEP)
401 (PAD_CFG1_PULL_NATIVE | PAD_CFG1_IOSSTATE_TX_LAST_RXE)
403 GPIO_75 /* I2S1_BCLK -- PCH_WP */
404 (PAD_CFG0_MODE_GPIO | PAD_CFG0_LOGICAL_RESET_DEEP)
405 (PAD_CFG1_PULL_UP_20K | PAD_CFG1_IOSSTATE_TXD_RXE)
408 GPIO_128 /* LPSS_I2C2_SDA */
409 (PAD_CFG0_MODE_NF1 | PAD_CFG0_LOGICAL_RESET_DEEP)
410 (PAD_CFG1_PULL_UP_2K | PAD_CFG1_IOSSTATE_TX_LAST_RXE)
411 GPIO_129 /* LPSS_I2C2_SCL */
412 (PAD_CFG0_MODE_NF1 | PAD_CFG0_LOGICAL_RESET_DEEP)
413 (PAD_CFG1_PULL_UP_2K | PAD_CFG1_IOSSTATE_TX_LAST_RXE)
414 GPIO_28 /* TPM IRQ */
415 (PAD_CFG0_MODE_GPIO | PAD_CFG0_LOGICAL_RESET_DEEP |
416 PAD_CFG0_TX_DISABLE | PAD_CFG0_ROUTE_IOAPIC |
417 PAD_CFG0_TRIG_LEVEL | PAD_CFG0_RX_POL_INVERT)
418 (PAD_CFG1_PULL_NONE | PAD_CFG1_IOSSTATE_TXD_RXE)
421 * WLAN_PE_RST - default to deasserted just in case FSP
424 GPIO_122 /* SIO_SPI_2_RXD */
425 (PAD_CFG0_MODE_GPIO | PAD_CFG0_LOGICAL_RESET_DEEP |
426 PAD_CFG0_RX_DISABLE | 0)
427 (PAD_CFG1_PULL_NONE | PAD_CFG1_IOSSTATE_TX_LAST_RXE)
430 PAD_CFG_NF(LPC_ILB_SERIRQ, UP_20K, DEEP, NF1) /* LPC_SERIRQ */
431 PAD_CFG_NF(LPC_CLKOUT0, NONE, DEEP, NF1) /* LPC_CLKOUT0 */
432 PAD_CFG_NF(LPC_CLKOUT1, UP_20K, DEEP, NF1)
433 PAD_CFG_NF(LPC_AD0, UP_20K, DEEP, NF1) /* LPC_AD0 */
434 PAD_CFG_NF(LPC_AD1, UP_20K, DEEP, NF1) /* LPC_AD1 */
435 PAD_CFG_NF(LPC_AD2, UP_20K, DEEP, NF1) /* LPC_AD2 */
436 PAD_CFG_NF(LPC_AD3, UP_20K, DEEP, NF1) /* LPC_AD3 */
437 PAD_CFG_NF(LPC_CLKRUNB, UP_20K, DEEP, NF1) /* LPC_CLKRUN_N */
438 PAD_CFG_NF(LPC_FRAMEB, NATIVE, DEEP, NF1) /* LPC_FRAME_N */
441 fspm,package = <PACKAGE_BGA>;
442 fspm,profile = <PROFILE_LPDDR4_2400_24_22_22>;
443 fspm,memory-down = <MEMORY_DOWN_YES>;
444 fspm,scrambler-support = <1>;
445 fspm,interleaved-mode = <INTERLEAVED_MODE_ENABLE>;
446 fspm,channel-hash-mask = <0x36>;
447 fspm,slice-hash-mask = <0x9>;
448 fspm,dual-rank-support-enable = <1>;
449 fspm,low-memory-max-value = <2048>;
450 fspm,ch0-rank-enable = <1>;
451 fspm,ch0-device-width = <CHX_DEVICE_WIDTH_X16>;
452 fspm,ch0-dram-density = <CHX_DEVICE_DENSITY_8GB>;
453 fspm,ch0-option = <(CHX_OPTION_RANK_INTERLEAVING |
454 CHX_OPTION_BANK_ADDRESS_HASHING_ENABLE)>;
455 fspm,ch0-odt-config = <CHX_ODT_CONFIG_DDR4_CA_ODT>;
456 fspm,ch1-rank-enable = <1>;
457 fspm,ch1-device-width = <CHX_DEVICE_WIDTH_X16>;
458 fspm,ch1-dram-density = <CHX_DEVICE_DENSITY_8GB>;
459 fspm,ch1-option = <(CHX_OPTION_RANK_INTERLEAVING |
460 CHX_OPTION_BANK_ADDRESS_HASHING_ENABLE)>;
461 fspm,ch1-odt-config = <CHX_ODT_CONFIG_DDR4_CA_ODT>;
462 fspm,ch2-rank-enable = <1>;
463 fspm,ch2-device-width = <CHX_DEVICE_WIDTH_X16>;
464 fspm,ch2-dram-density = <CHX_DEVICE_DENSITY_8GB>;
465 fspm,ch2-option = <(CHX_OPTION_RANK_INTERLEAVING |
466 CHX_OPTION_BANK_ADDRESS_HASHING_ENABLE)>;
467 fspm,ch2-odt-config = <CHX_ODT_CONFIG_DDR4_CA_ODT>;
468 fspm,ch3-rank-enable = <1>;
469 fspm,ch3-device-width = <CHX_DEVICE_WIDTH_X16>;
470 fspm,ch3-dram-density = <CHX_DEVICE_DENSITY_8GB>;
471 fspm,ch3-option = <(CHX_OPTION_RANK_INTERLEAVING |
472 CHX_OPTION_BANK_ADDRESS_HASHING_ENABLE)>;
473 fspm,ch3-odt-config = <CHX_ODT_CONFIG_DDR4_CA_ODT>;
474 fspm,fspm,skip-cse-rbp = <1>;
476 fspm,ch-bit-swizzling = /bits/ 8 <
479 /* DQA[0:7] pins of LPDDR4 module */
481 /* DQA[8:15] pins of LPDDR4 module */
482 12 10 11 13 14 8 9 15
483 /* DQB[0:7] pins of LPDDR4 module with offset of 16 */
484 16 22 23 20 18 17 19 21
485 /* DQB[7:15] pins of LPDDR4 module with offset of 16 */
486 30 28 29 25 24 26 27 31
489 /* DQA[0:7] pins of LPDDR4 module */
491 /* DQA[8:15] pins of LPDDR4 module */
492 9 14 12 13 10 11 8 15
493 /* DQB[0:7] pins of LPDDR4 module with offset of 16 */
494 20 22 23 16 19 17 18 21
495 /* DQB[7:15] pins of LPDDR4 module with offset of 16 */
496 28 24 26 27 29 30 31 25
500 /* DQA[0:7] pins of LPDDR4 module */
502 /* DQA[8:15] pins of LPDDR4 module */
503 11 10 8 9 12 15 13 14
504 /* DQB[0:7] pins of LPDDR4 module with offset of 16 */
505 17 23 19 16 21 22 20 18
506 /* DQB[7:15] pins of LPDDR4 module with offset of 16 */
507 31 29 26 25 28 27 24 30
511 /* DQA[0:7] pins of LPDDR4 module */
513 /* DQA[8:15] pins of LPDDR4 module */
514 15 9 8 11 14 13 12 10
515 /* DQB[0:7] pins of LPDDR4 module with offset of 16 */
516 20 23 22 21 18 19 16 17
517 /* DQB[7:15] pins of LPDDR4 module with offset of 16 */
518 25 28 30 31 26 27 24 29>;
522 u-boot,dm-pre-proper;
524 fsps,ish-enable = <0>;
525 fsps,enable-sata = <0>;
526 fsps,pcie-root-port-en = [00 00 00 00 00 01];
527 fsps,pcie-rp-hot-plug = [00 00 00 00 00 01];
528 fsps,i2c6-enable = <I2CX_ENABLE_DISABLED>;
529 fsps,i2c7-enable = <I2CX_ENABLE_DISABLED>;
530 fsps,hsuart3-enable = <HSUARTX_ENABLE_DISABLED>;
531 fsps,spi1-enable = <SPIX_ENABLE_DISABLED>;
532 fsps,spi2-enable = <SPIX_ENABLE_DISABLED>;
533 fsps,sdio-enabled = <0>;
535 /* Disable unused clkreq of PCIe root ports */
536 fsps,pcie-rp-clk-req-number = /bits/ 8 <0 /* wifi/bt */
545 * If the Board has PERST_0 signal, assign the GPIO
546 * If the Board does not have PERST_0, assign GPIO_PRT0_UDEF
548 * This are not used yet, so comment them out for now.
550 * prt0-gpio = <GPIO_122>;
552 * GPIO for SD card detect
553 * sdcard-cd-gpio = <GPIO_177>;
557 * Order is emmc-tx-data-cntl1, emmc-tx-data-cntl2,
558 * emmc-rx-cmd-data-cntl1, emmc-rx-cmd-data-cntl2
560 * EMMC TX DATA Delay 1
561 * Refer to EDS-Vol2-22.3
562 * [14:8] steps of delay for HS400, each 125ps
563 * [6:0] steps of delay for SDR104/HS200, each 125ps
566 * EMMC TX DATA Delay 2
567 * Refer to EDS-Vol2-22.3.
568 * [30:24] steps of delay for SDR50, each 125ps
569 * [22:16] steps of delay for DDR50, each 125ps
570 * [14:8] steps of delay for SDR25/HS50, each 125ps
571 * [6:0] steps of delay for SDR12, each 125ps
575 * EMMC RX CMD/DATA Delay 1
576 * Refer to EDS-Vol2-22.3.
577 * [30:24] steps of delay for SDR50, each 125ps
578 * [22:16] steps of delay for DDR50, each 125ps
579 * [14:8] steps of delay for SDR25/HS50, each 125ps
580 * [6:0] steps of delay for SDR12, each 125ps
584 * EMMC RX CMD/DATA Delay 2
585 * Refer to EDS-Vol2-22.3.
586 * [17:16] stands for Rx Clock before Output Buffer
587 * [14:8] steps of delay for Auto Tuning Mode, each 125ps
588 * [6:0] steps of delay for HS200, each 125ps
592 fsps,emmc-tx-data-cntl1 = <0x0c16>;
593 fsps,emmc-tx-data-cntl2 = <0x28162828>;
594 fsps,emmc-rx-cmd-data-cntl1 = <0x00181717>;
595 fsps,emmc-rx-cmd-data-cntl2 = <0x10008>;
597 /* Enable Audio Clock and Power gating */
598 fsps,hd-audio-clk-gate = <1>;
599 fsps,hd-audio-pwr-gate = <1>;
600 fsps,bios-cfg-lock-down = <1>;
602 /* Enable lpss s0ix */
603 fsps,lpss-s0ix-enable = <1>;
605 fsps,skip-mp-init = <1>;
609 fsps,port-usb20-per-port-pe-txi-set = [07 07 06 06 07 07 07 01];
610 fsps,port-usb20-per-port-txi-set = [00 02 00 00 00 00 00 03];
613 * TODO(sjg@chromium.org): Move this to the I2C nodes
614 * Intel Common SoC Config
615 *+-------------------+---------------------------+
617 *+-------------------+---------------------------+
620 *| I2C3 | Touchscreen |
622 *| I2C5 | Digitizer |
623 *+-------------------+---------------------------+
625 common_soc_config" = "{
627 .speed = I2C_SPEED_FAST,
633 .speed = I2C_SPEED_FAST,
638 .speed = I2C_SPEED_FAST,
643 .speed = I2C_SPEED_FAST,
646 .data_hold_time_ns = 350,
649 .speed = I2C_SPEED_FAST,
656 /* Minimum SLP S3 assertion width 28ms */
657 slp-s3-assertion-width-usecs = <28000>;
660 /* PCIE_WAKE[0:3]_N */
661 PAD_CFG_GPI_SCI_LOW(GPIO_205, UP_20K, DEEP, EDGE_SINGLE) /* WLAN */
662 PAD_CFG_GPI(GPIO_206, UP_20K, DEEP) /* Unused */
663 PAD_CFG_GPI(GPIO_207, UP_20K, DEEP) /* Unused */
664 PAD_CFG_GPI(GPIO_208, UP_20K, DEEP) /* Unused */
667 PAD_CFG_NF(GPIO_156, DN_20K, DEEP, NF1) /* EMMC_CLK */
668 PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_157, UP_20K, DEEP, NF1, HIZCRX1, DISPUPD) /* EMMC_D0 */
669 PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_158, UP_20K, DEEP, NF1, HIZCRX1, DISPUPD) /* EMMC_D1 */
670 PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_159, UP_20K, DEEP, NF1, HIZCRX1, DISPUPD) /* EMMC_D2 */
671 PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_160, UP_20K, DEEP, NF1, HIZCRX1, DISPUPD) /* EMMC_D3 */
672 PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_161, UP_20K, DEEP, NF1, HIZCRX1, DISPUPD) /* EMMC_D4 */
673 PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_162, UP_20K, DEEP, NF1, HIZCRX1, DISPUPD) /* EMMC_D5 */
674 PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_163, UP_20K, DEEP, NF1, HIZCRX1, DISPUPD) /* EMMC_D6 */
675 PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_164, UP_20K, DEEP, NF1, HIZCRX1, DISPUPD) /* EMMC_D7 */
676 PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_165, UP_20K, DEEP, NF1, HIZCRX1, DISPUPD) /* EMMC_CMD */
677 PAD_CFG_NF(GPIO_182, DN_20K, DEEP, NF1) /* EMMC_RCLK */
680 PAD_CFG_GPI(GPIO_166, UP_20K, DEEP) /* SDIO_CLK */
681 PAD_CFG_GPI(GPIO_167, UP_20K, DEEP) /* SDIO_D0 */
682 /* Configure SDIO to enable power gating */
683 PAD_CFG_NF(GPIO_168, UP_20K, DEEP, NF1) /* SDIO_D1 */
684 PAD_CFG_GPI(GPIO_169, UP_20K, DEEP) /* SDIO_D2 */
685 PAD_CFG_GPI(GPIO_170, UP_20K, DEEP) /* SDIO_D3 */
686 PAD_CFG_GPI(GPIO_171, UP_20K, DEEP) /* SDIO_CMD */
689 /* Pull down clock by 20K */
690 PAD_CFG_NF(GPIO_172, DN_20K, DEEP, NF1) /* SDCARD_CLK */
691 PAD_CFG_NF(GPIO_173, UP_20K, DEEP, NF1) /* SDCARD_D0 */
692 PAD_CFG_NF(GPIO_174, UP_20K, DEEP, NF1) /* SDCARD_D1 */
693 PAD_CFG_NF(GPIO_175, UP_20K, DEEP, NF1) /* SDCARD_D2 */
694 PAD_CFG_NF(GPIO_176, UP_20K, DEEP, NF1) /* SDCARD_D3 */
695 /* Card detect is active LOW with external pull up */
696 PAD_CFG_NF(GPIO_177, NONE, DEEP, NF1) /* SDCARD_CD_N */
697 PAD_CFG_NF(GPIO_178, UP_20K, DEEP, NF1) /* SDCARD_CMD */
698 /* CLK feedback, internal signal, needs 20K pull down */
699 PAD_CFG_NF(GPIO_179, DN_20K, DEEP, NF1) /* SDCARD_CLK_FB */
700 /* No h/w write proect for uSD cards, pull down by 20K */
701 PAD_CFG_NF(GPIO_186, DN_20K, DEEP, NF1) /* SDCARD_LVL_WP */
702 /* EN_SD_SOCKET_PWR_L for SD slot power control. Default on */
703 PAD_CFG_GPO(GPIO_183, 0, DEEP) /* SDIO_PWR_DOWN_N */
705 /* SMBus -- unused */
706 PAD_CFG_GPI(SMB_ALERTB, UP_20K, DEEP) /* SMB_ALERT _N */
707 PAD_CFG_GPI(SMB_CLK, UP_20K, DEEP) /* SMB_CLK */
708 PAD_CFG_GPI(SMB_DATA, UP_20K, DEEP) /* SMB_DATA */
711 PAD_CFG_NF(LPC_ILB_SERIRQ, UP_20K, DEEP, NF1) /* LPC_SERIRQ */
712 PAD_CFG_NF(LPC_CLKOUT0, NONE, DEEP, NF1) /* LPC_CLKOUT0 */
713 PAD_CFG_NF(LPC_CLKOUT1, UP_20K, DEEP, NF1)
714 PAD_CFG_NF(LPC_AD0, UP_20K, DEEP, NF1) /* LPC_AD0 */
715 PAD_CFG_NF(LPC_AD1, UP_20K, DEEP, NF1) /* LPC_AD1 */
716 PAD_CFG_NF(LPC_AD2, UP_20K, DEEP, NF1) /* LPC_AD2 */
717 PAD_CFG_NF(LPC_AD3, UP_20K, DEEP, NF1) /* LPC_AD3 */
718 PAD_CFG_NF(LPC_CLKRUNB, UP_20K, DEEP, NF1) /* LPC_CLKRUN_N */
719 PAD_CFG_NF(LPC_FRAMEB, NATIVE, DEEP, NF1) /* LPC_FRAME_N */
722 PAD_CFG_NF(GPIO_124, UP_2K, DEEP, NF1) /* LPSS_I2C0_SDA */
723 PAD_CFG_NF(GPIO_125, UP_2K, DEEP, NF1) /* LPSS_I2C0_SCL */
725 /* I2C1 - NFC with external pulls */
726 PAD_CFG_NF(GPIO_126, NONE, DEEP, NF1) /* LPSS_I2C1_SDA */
727 PAD_CFG_NF(GPIO_127, NONE, DEEP, NF1) /* LPSS_I2C1_SCL */
730 PAD_CFG_NF(GPIO_128, UP_2K, DEEP, NF1) /* LPSS_I2C2_SDA */
731 PAD_CFG_NF(GPIO_129, UP_2K, DEEP, NF1) /* LPSS_I2C2_SCL */
734 PAD_CFG_NF(GPIO_130, UP_2K, DEEP, NF1) /* LPSS_I2C3_SDA */
735 PAD_CFG_NF(GPIO_131, UP_2K, DEEP, NF1) /* LPSS_I2C3_SCL */
737 /* I2C4 - trackpad */
739 PAD_CFG_NF_IOSSTATE(GPIO_132, UP_2K, DEEP, NF1, HIZCRX1)
741 PAD_CFG_NF_IOSSTATE(GPIO_133, UP_2K, DEEP, NF1, HIZCRX1)
743 /* I2C5 -- pen with external pulls */
744 PAD_CFG_NF(GPIO_134, NONE, DEEP, NF1) /* LPSS_I2C5_SDA */
745 PAD_CFG_NF(GPIO_135, NONE, DEEP, NF1) /* LPSS_I2C5_SCL */
747 /* I2C6-7 -- unused */
748 PAD_CFG_GPI(GPIO_136, UP_20K, DEEP) /* LPSS_I2C6_SDA */
749 PAD_CFG_GPI(GPIO_137, UP_20K, DEEP) /* LPSS_I2C6_SCL */
750 PAD_CFG_GPI(GPIO_138, UP_20K, DEEP) /* LPSS_I2C7_SDA */
751 PAD_CFG_GPI(GPIO_139, UP_20K, DEEP) /* LPSS_I2C7_SCL */
753 /* Audio Amp - I2S6 */
754 PAD_CFG_NF(GPIO_146, NATIVE, DEEP, NF2) /* ISH_GPIO_0 - I2S6_BCLK */
755 PAD_CFG_NF(GPIO_147, NATIVE, DEEP, NF2) /* ISH_GPIO_1 - I2S6_WS_SYNC */
756 PAD_CFG_GPI(GPIO_148, UP_20K, DEEP) /* ISH_GPIO_2 - unused */
757 PAD_CFG_NF(GPIO_149, NATIVE, DEEP, NF2) /* ISH_GPIO_3 - I2S6_SDO */
760 PAD_CFG_GPO(GPIO_150, 1, DEEP) /* ISH_GPIO_4 */
762 PAD_CFG_GPI(GPIO_151, UP_20K, DEEP) /* ISH_GPIO_5 - unused */
765 PAD_CFG_GPO(GPIO_152, 1, DEEP) /* ISH_GPIO_6 */
767 PAD_CFG_GPI(GPIO_153, UP_20K, DEEP) /* ISH_GPIO_7 - unused */
768 PAD_CFG_GPI(GPIO_154, UP_20K, DEEP) /* ISH_GPIO_8 - unused */
769 PAD_CFG_GPI(GPIO_155, UP_20K, DEEP) /* ISH_GPIO_9 - unused */
771 /* PCIE_CLKREQ[0:3]_N */
772 PAD_CFG_NF(GPIO_209, NONE, DEEP, NF1) /* WLAN with external pull */
773 PAD_CFG_GPI(GPIO_210, UP_20K, DEEP) /* unused */
774 PAD_CFG_GPI(GPIO_211, UP_20K, DEEP) /* unused */
775 PAD_CFG_GPI(GPIO_212, UP_20K, DEEP) /* unused */
777 /* OSC_CLK_OUT_[0:4] -- unused */
778 PAD_CFG_GPI(OSC_CLK_OUT_0, UP_20K, DEEP)
779 PAD_CFG_GPI(OSC_CLK_OUT_1, UP_20K, DEEP)
780 PAD_CFG_GPI(OSC_CLK_OUT_2, UP_20K, DEEP)
781 PAD_CFG_GPI(OSC_CLK_OUT_3, UP_20K, DEEP)
782 PAD_CFG_GPI(OSC_CLK_OUT_4, UP_20K, DEEP)
785 PAD_CFG_GPI(PMU_AC_PRESENT, UP_20K, DEEP) /* PMU_AC_PRESENT - unused */
786 PAD_CFG_NF(PMU_BATLOW_B, UP_20K, DEEP, NF1) /* PMU_BATLOW_N */
787 PAD_CFG_NF(PMU_PLTRST_B, NONE, DEEP, NF1) /* PMU_PLTRST_N */
788 PAD_CFG_NF(PMU_PWRBTN_B, UP_20K, DEEP, NF1) /* PMU_PWRBTN_N */
789 PAD_CFG_NF(PMU_RESETBUTTON_B, NONE, DEEP, NF1) /* PMU_RSTBTN_N */
790 PAD_CFG_NF_IOSSTATE(PMU_SLP_S0_B, NONE, DEEP, NF1, IGNORE) /* PMU_SLP_S0_N */
791 PAD_CFG_NF(PMU_SLP_S3_B, NONE, DEEP, NF1) /* PMU_SLP_S3_N */
792 PAD_CFG_NF(PMU_SLP_S4_B, NONE, DEEP, NF1) /* PMU_SLP_S4_N */
793 PAD_CFG_NF(PMU_SUSCLK, NONE, DEEP, NF1) /* PMU_SUSCLK */
794 PAD_CFG_GPO(PMU_WAKE_B, 1, DEEP) /* EN_PP3300_EMMC */
795 PAD_CFG_NF(SUS_STAT_B, NONE, DEEP, NF1) /* SUS_STAT_N */
796 PAD_CFG_NF(SUSPWRDNACK, NONE, DEEP, NF1) /* SUSPWRDNACK */
798 /* DDI[0:1] SDA and SCL -- unused */
799 PAD_CFG_GPI(GPIO_187, UP_20K, DEEP) /* HV_DDI0_DDC_SDA */
800 PAD_CFG_GPI(GPIO_188, UP_20K, DEEP) /* HV_DDI0_DDC_SCL */
801 PAD_CFG_GPI(GPIO_189, UP_20K, DEEP) /* HV_DDI1_DDC_SDA */
802 PAD_CFG_GPI(GPIO_190, UP_20K, DEEP) /* HV_DDI1_DDC_SCL */
804 /* MIPI I2C -- unused */
805 PAD_CFG_GPI(GPIO_191, UP_20K, DEEP) /* MIPI_I2C_SDA */
806 PAD_CFG_GPI(GPIO_192, UP_20K, DEEP) /* MIPI_I2C_SCL */
808 /* Panel 0 control */
809 PAD_CFG_NF(GPIO_193, NATIVE, DEEP, NF1) /* PNL0_VDDEN */
810 PAD_CFG_NF(GPIO_194, NATIVE, DEEP, NF1) /* PNL0_BKLTEN */
811 PAD_CFG_NF(GPIO_195, NATIVE, DEEP, NF1) /* PNL0_BKLTCTL */
813 /* Panel 1 control -- unused */
814 PAD_CFG_NF(GPIO_196, NATIVE, DEEP, NF1) /* PNL1_VDDEN */
815 PAD_CFG_NF(GPIO_197, NATIVE, DEEP, NF1) /* PNL1_BKLTEN */
816 PAD_CFG_NF(GPIO_198, NATIVE, DEEP, NF1) /* PNL1_BKLTCTL */
818 /* Hot plug detect */
819 PAD_CFG_NF(GPIO_199, UP_20K, DEEP, NF2) /* HV_DDI1_HPD */
820 PAD_CFG_NF(GPIO_200, UP_20K, DEEP, NF2) /* HV_DDI0_HPD */
822 /* MDSI signals -- unused */
823 PAD_CFG_GPI(GPIO_201, UP_20K, DEEP) /* MDSI_A_TE */
824 PAD_CFG_GPI(GPIO_202, UP_20K, DEEP) /* MDSI_A_TE */
826 /* USB overcurrent pins */
827 PAD_CFG_NF(GPIO_203, UP_20K, DEEP, NF1) /* USB_OC0_N */
828 PAD_CFG_NF(GPIO_204, UP_20K, DEEP, NF1) /* USB_OC1_N */
830 /* PMC SPI -- almost entirely unused */
831 PAD_CFG_GPI(PMC_SPI_FS0, UP_20K, DEEP)
832 PAD_CFG_NF(PMC_SPI_FS1, UP_20K, DEEP, NF2) /* HV_DDI2_HPD -- EDP HPD */
833 PAD_CFG_GPI(PMC_SPI_FS2, UP_20K, DEEP)
834 PAD_CFG_GPI(PMC_SPI_RXD, UP_20K, DEEP)
835 PAD_CFG_GPI(PMC_SPI_TXD, UP_20K, DEEP)
836 PAD_CFG_GPI(PMC_SPI_CLK, UP_20K, DEEP)
838 /* PMIC Signals Unused signals related to an old PMIC interface */
839 PAD_CFG_NF_IOSSTATE(PMIC_RESET_B, NATIVE, DEEP, NF1, IGNORE) /* PMIC_RESET_B */
840 PAD_CFG_GPI(GPIO_213, NONE, DEEP) /* unused external pull */
841 PAD_CFG_GPI(GPIO_214, UP_20K, DEEP) /* unused */
842 PAD_CFG_GPI(GPIO_215, UP_20K, DEEP) /* unused */
843 PAD_CFG_NF(PMIC_THERMTRIP_B, UP_20K, DEEP, NF1) /* THERMTRIP_N */
844 PAD_CFG_GPI(PMIC_STDBY, UP_20K, DEEP) /* unused */
845 PAD_CFG_NF(PROCHOT_B, UP_20K, DEEP, NF1) /* PROCHOT_N */
846 PAD_CFG_NF(PMIC_I2C_SCL, UP_1K, DEEP, NF1) /* PMIC_I2C_SCL */
847 PAD_CFG_NF(PMIC_I2C_SDA, UP_1K, DEEP, NF1) /* PMIC_I2C_SDA */
849 /* I2S1 -- largely unused */
850 PAD_CFG_GPI(GPIO_74, UP_20K, DEEP) /* I2S1_MCLK */
851 PAD_CFG_GPI(GPIO_75, UP_20K, DEEP) /* I2S1_BCLK -- PCH_WP */
852 PAD_CFG_GPO(GPIO_76, 0, DEEP) /* I2S1_WS_SYNC -- SPK_PA_EN */
853 PAD_CFG_GPI(GPIO_77, UP_20K, DEEP) /* I2S1_SDI */
854 PAD_CFG_GPO(GPIO_78, 1, DEEP) /* I2S1_SDO -- EN_PP3300_DX_LTE_SOC */
857 /* AVS_DMIC_CLK_A1 */
858 PAD_CFG_NF_IOSSTATE(GPIO_79, NATIVE, DEEP, NF1, IGNORE)
859 PAD_CFG_NF(GPIO_80, NATIVE, DEEP, NF1) /* AVS_DMIC_CLK_B1 */
860 PAD_CFG_NF(GPIO_81, NATIVE, DEEP, NF1) /* AVS_DMIC_DATA_1 */
861 PAD_CFG_GPI(GPIO_82, DN_20K, DEEP) /* unused -- strap */
862 PAD_CFG_NF(GPIO_83, NATIVE, DEEP, NF1) /* AVS_DMIC_DATA_2 */
864 /* I2S2 -- Headset amp */
865 PAD_CFG_NF(GPIO_84, NATIVE, DEEP, NF1) /* AVS_I2S2_MCLK */
866 PAD_CFG_NF(GPIO_85, NATIVE, DEEP, NF1) /* AVS_I2S2_BCLK */
867 PAD_CFG_NF(GPIO_86, NATIVE, DEEP, NF1) /* AVS_I2S2_SW_SYNC */
868 PAD_CFG_NF(GPIO_87, NATIVE, DEEP, NF1) /* AVS_I2S2_SDI */
869 PAD_CFG_NF(GPIO_88, NATIVE, DEEP, NF1) /* AVS_I2S2_SDO */
871 /* I2S3 -- largely unused */
872 PAD_CFG_GPI(GPIO_89, UP_20K, DEEP) /* unused */
873 PAD_CFG_GPI(GPIO_90, UP_20K, DEEP) /* GPS_HOST_WAKE */
874 PAD_CFG_GPO(GPIO_91, 1, DEEP) /* GPS_EN */
875 PAD_CFG_GPI(GPIO_92, DN_20K, DEEP) /* unused -- strap */
878 PAD_CFG_NF_IOSSTATE(GPIO_97, NATIVE, DEEP, NF1, IGNORE) /* FST_SPI_CS0_B */
879 PAD_CFG_GPI(GPIO_98, UP_20K, DEEP) /* FST_SPI_CS1_B -- unused */
880 PAD_CFG_NF_IOSSTATE(GPIO_99, NATIVE, DEEP, NF1, IGNORE) /* FST_SPI_MOSI_IO0 */
881 PAD_CFG_NF_IOSSTATE(GPIO_100, NATIVE, DEEP, NF1, IGNORE) /* FST_SPI_MISO_IO1 */
882 PAD_CFG_GPI(GPIO_101, NONE, DEEP) /* FST_IO2 -- MEM_CONFIG0 */
883 PAD_CFG_GPI(GPIO_102, NONE, DEEP) /* FST_IO3 -- MEM_CONFIG1 */
884 PAD_CFG_NF_IOSSTATE(GPIO_103, NATIVE, DEEP, NF1, IGNORE) /* FST_SPI_CLK */
885 PAD_CFG_NF_IOSSTATE(FST_SPI_CLK_FB, NATIVE, DEEP, NF1, IGNORE) /* FST_SPI_CLK_FB */
886 PAD_CFG_NF_IOSSTATE(GPIO_106, NATIVE, DEEP, NF3, IGNORE) /* FST_SPI_CS2_N */
888 /* SIO_SPI_0 - Used for FP */
889 PAD_CFG_NF(GPIO_104, NATIVE, DEEP, NF1) /* SIO_SPI_0_CLK */
890 PAD_CFG_NF(GPIO_105, NATIVE, DEEP, NF1) /* SIO_SPI_0_FS0 */
891 PAD_CFG_NF(GPIO_109, NATIVE, DEEP, NF1) /* SIO_SPI_0_RXD */
892 PAD_CFG_NF(GPIO_110, NATIVE, DEEP, NF1) /* SIO_SPI_0_TXD */
894 /* SIO_SPI_1 -- largely unused */
895 PAD_CFG_GPI(GPIO_111, UP_20K, DEEP) /* SIO_SPI_1_CLK */
896 PAD_CFG_GPI(GPIO_112, UP_20K, DEEP) /* SIO_SPI_1_FS0 */
897 PAD_CFG_GPI(GPIO_113, UP_20K, DEEP) /* SIO_SPI_1_FS1 */
898 /* Headset interrupt */
899 PAD_CFG_GPI_APIC_LOW(GPIO_116, NONE, DEEP) /* SIO_SPI_1_RXD */
900 PAD_CFG_GPI(GPIO_117, UP_20K, DEEP) /* SIO_SPI_1_TXD */
902 /* SIO_SPI_2 -- unused */
903 PAD_CFG_GPI(GPIO_118, UP_20K, DEEP) /* SIO_SPI_2_CLK */
904 PAD_CFG_GPI(GPIO_119, UP_20K, DEEP) /* SIO_SPI_2_FS0 */
905 PAD_CFG_GPI(GPIO_120, UP_20K, DEEP) /* SIO_SPI_2_FS1 */
906 PAD_CFG_GPI(GPIO_121, UP_20K, DEEP) /* SIO_SPI_2_FS2 */
907 /* WLAN_PE_RST - default to deasserted */
908 PAD_CFG_GPO(GPIO_122, 0, DEEP) /* SIO_SPI_2_RXD */
909 PAD_CFG_GPI(GPIO_123, UP_20K, DEEP) /* SIO_SPI_2_TXD */
912 PAD_CFG_GPI(GPIO_0, UP_20K, DEEP)
913 PAD_CFG_GPI(GPIO_1, UP_20K, DEEP)
914 PAD_CFG_GPI(GPIO_2, UP_20K, DEEP)
915 PAD_CFG_GPI_SCI_HIGH(GPIO_3, DN_20K, DEEP, LEVEL) /* FP_INT */
916 PAD_CFG_GPI(GPIO_4, UP_20K, DEEP)
917 PAD_CFG_GPI(GPIO_5, UP_20K, DEEP)
918 PAD_CFG_GPI(GPIO_6, UP_20K, DEEP)
919 PAD_CFG_GPI(GPIO_7, UP_20K, DEEP)
920 PAD_CFG_GPI(GPIO_8, UP_20K, DEEP)
922 PAD_CFG_GPI_APIC_LOW(GPIO_9, NONE, DEEP) /* dTPM IRQ */
923 PAD_CFG_GPI(GPIO_10, DN_20K, DEEP) /* Board phase enforcement */
924 PAD_CFG_GPI_SCI_LOW(GPIO_11, NONE, DEEP, EDGE_SINGLE) /* EC SCI */
925 PAD_CFG_GPI(GPIO_12, UP_20K, DEEP) /* unused */
926 PAD_CFG_GPI_APIC_LOW(GPIO_13, NONE, DEEP) /* PEN_INT_ODL */
927 PAD_CFG_GPI_APIC_HIGH(GPIO_14, DN_20K, DEEP) /* FP_INT */
928 PAD_CFG_GPI_SCI_LOW(GPIO_15, NONE, DEEP, EDGE_SINGLE) /* TRACKPAD_INT_1V8_ODL */
929 PAD_CFG_GPI(GPIO_16, UP_20K, DEEP) /* unused */
930 PAD_CFG_GPI(GPIO_17, UP_20K, DEEP) /* 1 vs 4 DMIC config */
931 PAD_CFG_GPI_APIC_LOW(GPIO_18, NONE, DEEP) /* Trackpad IRQ */
932 PAD_CFG_GPI(GPIO_19, UP_20K, DEEP) /* unused */
933 PAD_CFG_GPI_APIC_LOW(GPIO_20, UP_20K, DEEP) /* NFC IRQ */
934 PAD_CFG_GPI_APIC_LOW(GPIO_21, NONE, DEEP) /* Touch IRQ */
935 PAD_CFG_GPI_SCI_LOW(GPIO_22, NONE, DEEP, EDGE_SINGLE) /* EC wake */
936 PAD_CFG_GPI(GPIO_23, UP_20K, DEEP) /* unused */
937 PAD_CFG_GPI(GPIO_24, NONE, DEEP) /* PEN_PDCT_ODL */
938 PAD_CFG_GPI(GPIO_25, UP_20K, DEEP) /* unused */
939 PAD_CFG_GPI(GPIO_26, UP_20K, DEEP) /* unused */
940 PAD_CFG_GPI(GPIO_27, UP_20K, DEEP) /* unused */
941 PAD_CFG_GPI_APIC_LOW(GPIO_28, NONE, DEEP) /* TPM IRQ */
942 PAD_CFG_GPO(GPIO_29, 1, DEEP) /* FP reset */
943 PAD_CFG_GPI_APIC_LOW(GPIO_30, NONE, DEEP) /* KB IRQ */
944 PAD_CFG_GPO(GPIO_31, 0, DEEP) /* NFC FW DL */
945 PAD_CFG_NF(GPIO_32, NONE, DEEP, NF5) /* SUS_CLK2 */
946 PAD_CFG_GPI_APIC_LOW(GPIO_33, NONE, DEEP) /* PMIC IRQ */
947 PAD_CFG_GPI(GPIO_34, UP_20K, DEEP) /* unused */
948 PAD_CFG_GPO(GPIO_35, 0, DEEP) /* PEN_RESET - active high */
949 PAD_CFG_GPO(GPIO_36, 0, DEEP) /* touch reset */
950 PAD_CFG_GPI(GPIO_37, UP_20K, DEEP) /* unused */
953 PAD_CFG_GPI(GPIO_38, NONE, DEEP) /* LPSS_UART0_RXD - MEM_CONFIG2*/
954 /* Next 2 are straps */
955 PAD_CFG_GPI(GPIO_39, DN_20K, DEEP) /* LPSS_UART0_TXD - unused */
956 PAD_CFG_GPI(GPIO_40, DN_20K, DEEP) /* LPSS_UART0_RTS - unused */
957 PAD_CFG_GPI(GPIO_41, NONE, DEEP) /* LPSS_UART0_CTS - EC_IN_RW */
958 PAD_CFG_NF(GPIO_42, NATIVE, DEEP, NF1) /* LPSS_UART1_RXD */
959 PAD_CFG_NF(GPIO_43, NATIVE, DEEP, NF1) /* LPSS_UART1_TXD */
960 PAD_CFG_GPO(GPIO_44, 1, DEEP) /* GPS_RST_ODL */
961 PAD_CFG_GPI(GPIO_45, NONE, DEEP) /* LPSS_UART1_CTS - MEM_CONFIG3 */
962 PAD_CFG_NF(GPIO_46, NATIVE, DEEP, NF1) /* LPSS_UART2_RXD */
963 PAD_CFG_NF_IOSSTATE(GPIO_47, NATIVE, DEEP, NF1, TX1_RX_DCR_X0) /* UART2 TX */
964 PAD_CFG_GPI(GPIO_48, UP_20K, DEEP) /* LPSS_UART2_RTS - unused */
965 PAD_CFG_GPI_SMI_LOW(GPIO_49, NONE, DEEP, EDGE_SINGLE) /* LPSS_UART2_CTS - EC_SMI_L */
967 /* Camera interface -- completely unused */
968 PAD_CFG_GPI(GPIO_62, UP_20K, DEEP) /* GP_CAMERASB00 */
969 PAD_CFG_GPI(GPIO_63, UP_20K, DEEP) /* GP_CAMERASB01 */
970 PAD_CFG_GPI(GPIO_64, UP_20K, DEEP) /* GP_CAMERASB02 */
971 PAD_CFG_GPI(GPIO_65, UP_20K, DEEP) /* GP_CAMERASB03 */
972 PAD_CFG_GPI(GPIO_66, UP_20K, DEEP) /* GP_CAMERASB04 */
973 PAD_CFG_GPI(GPIO_67, UP_20K, DEEP) /* GP_CAMERASB05 */
974 PAD_CFG_GPI(GPIO_68, UP_20K, DEEP) /* GP_CAMERASB06 */
975 PAD_CFG_GPI(GPIO_69, UP_20K, DEEP) /* GP_CAMERASB07 */
976 PAD_CFG_GPI(GPIO_70, UP_20K, DEEP) /* GP_CAMERASB08 */
977 PAD_CFG_GPI(GPIO_71, UP_20K, DEEP) /* GP_CAMERASB09 */
978 PAD_CFG_GPI(GPIO_72, UP_20K, DEEP) /* GP_CAMERASB10 */
979 PAD_CFG_GPI(GPIO_73, UP_20K, DEEP) /* GP_CAMERASB11 */