1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>
8 #include <asm/arch-braswell/fsp/fsp_configs.h>
9 #include <dt-bindings/interrupt-router/intel-irq.h>
11 /include/ "skeleton.dtsi"
12 /include/ "serial.dtsi"
13 /include/ "reset.dtsi"
15 /include/ "tsc_timer.dtsi"
18 model = "Intel Cherry Hill";
19 compatible = "intel,cherryhill", "intel,braswell";
31 stdout-path = "/serial";
40 compatible = "cpu-x86";
47 compatible = "cpu-x86";
54 compatible = "cpu-x86";
61 compatible = "cpu-x86";
68 compatible = "pci-x86";
72 ranges = <0x02000000 0x0 0x80000000 0x80000000 0 0x40000000
73 0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000
74 0x01000000 0x0 0x2000 0x2000 0 0xe000>;
77 reg = <0x0000f800 0 0 0 0>;
78 compatible = "intel,pch9";
81 compatible = "intel,irq-router";
82 intel,pirq-config = "ibase";
83 intel,ibase-offset = <0x50>;
84 intel,pirq-link = <8 8>;
85 intel,pirq-mask = <0xdee0>;
86 intel,pirq-routing = <
87 /* Braswell PCI devices */
88 PCI_BDF(0, 2, 0) INTA PIRQA
89 PCI_BDF(0, 3, 0) INTA PIRQA
90 PCI_BDF(0, 11, 0) INTA PIRQA
91 PCI_BDF(0, 16, 0) INTA PIRQA
92 PCI_BDF(0, 17, 0) INTA PIRQA
93 PCI_BDF(0, 18, 0) INTA PIRQA
94 PCI_BDF(0, 19, 0) INTA PIRQA
95 PCI_BDF(0, 20, 0) INTA PIRQA
96 PCI_BDF(0, 21, 0) INTA PIRQA
97 PCI_BDF(0, 24, 0) INTA PIRQA
98 PCI_BDF(0, 24, 1) INTC PIRQC
99 PCI_BDF(0, 24, 2) INTD PIRQD
100 PCI_BDF(0, 24, 3) INTB PIRQB
101 PCI_BDF(0, 24, 4) INTA PIRQA
102 PCI_BDF(0, 24, 5) INTC PIRQC
103 PCI_BDF(0, 24, 6) INTD PIRQD
104 PCI_BDF(0, 24, 7) INTB PIRQB
105 PCI_BDF(0, 26, 0) INTA PIRQA
106 PCI_BDF(0, 27, 0) INTA PIRQA
107 PCI_BDF(0, 28, 0) INTA PIRQA
108 PCI_BDF(0, 28, 1) INTB PIRQB
109 PCI_BDF(0, 28, 2) INTC PIRQC
110 PCI_BDF(0, 28, 3) INTD PIRQD
111 PCI_BDF(0, 30, 0) INTA PIRQA
112 PCI_BDF(0, 30, 3) INTA PIRQA
113 PCI_BDF(0, 30, 4) INTA PIRQA
114 PCI_BDF(0, 31, 0) INTB PIRQB
115 PCI_BDF(0, 31, 3) INTB PIRQB
118 * PCIe root ports downstream
121 PCI_BDF(1, 0, 0) INTA PIRQA
122 PCI_BDF(1, 0, 0) INTB PIRQB
123 PCI_BDF(1, 0, 0) INTC PIRQC
124 PCI_BDF(1, 0, 0) INTD PIRQD
125 PCI_BDF(2, 0, 0) INTA PIRQB
126 PCI_BDF(2, 0, 0) INTB PIRQC
127 PCI_BDF(2, 0, 0) INTC PIRQD
128 PCI_BDF(2, 0, 0) INTD PIRQA
129 PCI_BDF(3, 0, 0) INTA PIRQC
130 PCI_BDF(3, 0, 0) INTB PIRQD
131 PCI_BDF(3, 0, 0) INTC PIRQA
132 PCI_BDF(3, 0, 0) INTD PIRQB
133 PCI_BDF(4, 0, 0) INTA PIRQD
134 PCI_BDF(4, 0, 0) INTB PIRQA
135 PCI_BDF(4, 0, 0) INTC PIRQB
136 PCI_BDF(4, 0, 0) INTD PIRQC
141 #address-cells = <1>;
143 compatible = "intel,ich9-spi";
147 #address-cells = <1>;
150 compatible = "macronix,mx25u6435f", "jedec,spi-nor";
151 memory-map = <0xff800000 0x00800000>;
153 label = "rw-mrc-cache";
154 reg = <0x005e0000 0x00010000>;
162 compatible = "intel,braswell-fsp";
164 compatible = "intel,braswell-fsp-memory";
165 fsp,mrc-init-tseg-size = <MRC_INIT_TSEG_SIZE_4MB>;
166 fsp,mrc-init-mmio-size = <MRC_INIT_MMIO_SIZE_2048MB>;
167 fsp,mrc-init-spd-addr1 = <0xa0>;
168 fsp,mrc-init-spd-addr2 = <0xa2>;
169 fsp,igd-dvmt50-pre-alloc = <IGD_DVMT50_PRE_ALLOC_32MB>;
170 fsp,aperture-size = <APERTURE_SIZE_256MB>;
171 fsp,gtt-size = <GTT_SIZE_1MB>;
173 fsp,memory-type = <DRAM_TYPE_DDR3>;
176 compatible = "intel,braswell-fsp-silicon";
177 fsp,sdcard-mode = <SDCARD_MODE_PCI>;
181 fsp,lpe-mode = <LPE_MODE_PCI>;
191 fsp,emmc-mode = <EMMC_MODE_PCI>;
192 fsp,sata-speed = <SATA_SPEED_GEN3>;
193 fsp,pmic-i2c-bus = <0>;
195 fsp,isp-pci-dev-config = <ISP_PCI_DEV_CONFIG_2>;
196 fsp,pnp-settings = <PNP_SETTING_POWER_AND_PERF>;
203 #include "microcode/m01406c2220.dtsi"
206 #include "microcode/m01406c3363.dtsi"
209 #include "microcode/m01406c440a.dtsi"