2 * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
4 * SPDX-License-Identifier: GPL-2.0+
9 #include <dt-bindings/gpio/x86-gpio.h>
10 #include <dt-bindings/interrupt-router/intel-irq.h>
12 /include/ "skeleton.dtsi"
13 /include/ "keyboard.dtsi"
14 /include/ "serial.dtsi"
16 /include/ "tsc_timer.dtsi"
19 model = "Intel Bayley Bay";
20 compatible = "intel,bayleybay", "intel,baytrail";
32 stdout-path = "/serial";
41 compatible = "intel,baytrail-cpu";
48 compatible = "intel,baytrail-cpu";
55 compatible = "intel,baytrail-cpu";
62 compatible = "intel,baytrail-cpu";
71 compatible = "intel,ich-spi";
76 compatible = "winbond,w25q64dw", "spi-flash";
77 memory-map = <0xff800000 0x00800000>;
79 label = "rw-mrc-cache";
80 reg = <0x006e0000 0x00010000>;
86 compatible = "intel,ich6-gpio";
93 compatible = "intel,ich6-gpio";
100 compatible = "intel,ich6-gpio";
107 compatible = "intel,ich6-gpio";
114 compatible = "intel,ich6-gpio";
121 compatible = "intel,ich6-gpio";
128 compatible = "pci-x86";
129 #address-cells = <3>;
132 ranges = <0x02000000 0x0 0x80000000 0x80000000 0 0x40000000
133 0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000
134 0x01000000 0x0 0x2000 0x2000 0 0xe000>;
137 reg = <0x0000f800 0 0 0 0>;
138 compatible = "intel,irq-router";
139 intel,pirq-config = "ibase";
140 intel,ibase-offset = <0x50>;
141 intel,pirq-link = <8 8>;
142 intel,pirq-mask = <0xdee0>;
143 intel,pirq-routing = <
144 /* BayTrail PCI devices */
145 PCI_BDF(0, 2, 0) INTA PIRQA
146 PCI_BDF(0, 3, 0) INTA PIRQA
147 PCI_BDF(0, 16, 0) INTA PIRQA
148 PCI_BDF(0, 17, 0) INTA PIRQA
149 PCI_BDF(0, 18, 0) INTA PIRQA
150 PCI_BDF(0, 19, 0) INTA PIRQA
151 PCI_BDF(0, 20, 0) INTA PIRQA
152 PCI_BDF(0, 21, 0) INTA PIRQA
153 PCI_BDF(0, 22, 0) INTA PIRQA
154 PCI_BDF(0, 23, 0) INTA PIRQA
155 PCI_BDF(0, 24, 0) INTA PIRQA
156 PCI_BDF(0, 24, 1) INTC PIRQC
157 PCI_BDF(0, 24, 2) INTD PIRQD
158 PCI_BDF(0, 24, 3) INTB PIRQB
159 PCI_BDF(0, 24, 4) INTA PIRQA
160 PCI_BDF(0, 24, 5) INTC PIRQC
161 PCI_BDF(0, 24, 6) INTD PIRQD
162 PCI_BDF(0, 24, 7) INTB PIRQB
163 PCI_BDF(0, 26, 0) INTA PIRQA
164 PCI_BDF(0, 27, 0) INTA PIRQA
165 PCI_BDF(0, 28, 0) INTA PIRQA
166 PCI_BDF(0, 28, 1) INTB PIRQB
167 PCI_BDF(0, 28, 2) INTC PIRQC
168 PCI_BDF(0, 28, 3) INTD PIRQD
169 PCI_BDF(0, 29, 0) INTA PIRQA
170 PCI_BDF(0, 30, 0) INTA PIRQA
171 PCI_BDF(0, 30, 1) INTD PIRQD
172 PCI_BDF(0, 30, 2) INTB PIRQB
173 PCI_BDF(0, 30, 3) INTC PIRQC
174 PCI_BDF(0, 30, 4) INTD PIRQD
175 PCI_BDF(0, 30, 5) INTB PIRQB
176 PCI_BDF(0, 31, 3) INTB PIRQB
178 /* PCIe root ports downstream interrupts */
179 PCI_BDF(1, 0, 0) INTA PIRQA
180 PCI_BDF(1, 0, 0) INTB PIRQB
181 PCI_BDF(1, 0, 0) INTC PIRQC
182 PCI_BDF(1, 0, 0) INTD PIRQD
183 PCI_BDF(2, 0, 0) INTA PIRQB
184 PCI_BDF(2, 0, 0) INTB PIRQC
185 PCI_BDF(2, 0, 0) INTC PIRQD
186 PCI_BDF(2, 0, 0) INTD PIRQA
187 PCI_BDF(3, 0, 0) INTA PIRQC
188 PCI_BDF(3, 0, 0) INTB PIRQD
189 PCI_BDF(3, 0, 0) INTC PIRQA
190 PCI_BDF(3, 0, 0) INTD PIRQB
191 PCI_BDF(4, 0, 0) INTA PIRQD
192 PCI_BDF(4, 0, 0) INTB PIRQA
193 PCI_BDF(4, 0, 0) INTC PIRQB
194 PCI_BDF(4, 0, 0) INTD PIRQC
200 compatible = "intel,baytrail-fsp";
201 fsp,mrc-init-tseg-size = <0>;
202 fsp,mrc-init-mmio-size = <0x800>;
203 fsp,mrc-init-spd-addr1 = <0xa0>;
204 fsp,mrc-init-spd-addr2 = <0xa2>;
205 fsp,emmc-boot-mode = <2>;
213 fsp,lpss-sio-enable-pci-mode;
225 fsp,igd-dvmt50-pre-alloc = <2>;
226 fsp,aperture-size = <2>;
228 fsp,serial-debug-port-address = <0x3f8>;
229 fsp,serial-debug-port-type = <1>;
230 fsp,scc-enable-pci-mode;
231 fsp,os-selection = <4>;
232 fsp,emmc45-ddr50-enabled;
233 fsp,emmc45-retune-timer-value = <8>;
239 #include "microcode/m0230671117.dtsi"
242 #include "microcode/m0130673322.dtsi"
245 #include "microcode/m0130679901.dtsi"