arch/x86/dts/bayleybay.dts

   1 /*
   2  * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 /dts-v1/;
   8
   9 #include <dt-bindings/gpio/x86-gpio.h>
  10 #include <dt-bindings/interrupt-router/intel-irq.h>
  11
  12 /include/ "skeleton.dtsi"
  13 /include/ "keyboard.dtsi"
  14 /include/ "serial.dtsi"
  15 /include/ "rtc.dtsi"
  16 /include/ "tsc_timer.dtsi"
  17
  18 / {
  19         model = "Intel Bayley Bay";
  20         compatible = "intel,bayleybay", "intel,baytrail";
  21
  22         aliases {
  23                 serial0 = &serial;
  24                 spi0 = "/spi";
  25         };
  26
  27         config {
  28                 silent_console = <0>;
  29         };
  30
  31         chosen {
  32                 stdout-path = "/serial";
  33         };
  34
  35         cpus {
  36                 #address-cells = <1>;
  37                 #size-cells = <0>;
  38
  39                 cpu@0 {
  40                         device_type = "cpu";
  41                         compatible = "intel,baytrail-cpu";
  42                         reg = <0>;
  43                         intel,apic-id = <0>;
  44                 };
  45
  46                 cpu@1 {
  47                         device_type = "cpu";
  48                         compatible = "intel,baytrail-cpu";
  49                         reg = <1>;
  50                         intel,apic-id = <2>;
  51                 };
  52
  53                 cpu@2 {
  54                         device_type = "cpu";
  55                         compatible = "intel,baytrail-cpu";
  56                         reg = <2>;
  57                         intel,apic-id = <4>;
  58                 };
  59
  60                 cpu@3 {
  61                         device_type = "cpu";
  62                         compatible = "intel,baytrail-cpu";
  63                         reg = <3>;
  64                         intel,apic-id = <6>;
  65                 };
  66         };
  67
  68         gpioa {
  69                 compatible = "intel,ich6-gpio";
  70                 u-boot,dm-pre-reloc;
  71                 reg = <0 0x20>;
  72                 bank-name = "A";
  73         };
  74
  75         gpiob {
  76                 compatible = "intel,ich6-gpio";
  77                 u-boot,dm-pre-reloc;
  78                 reg = <0x20 0x20>;
  79                 bank-name = "B";
  80         };
  81
  82         gpioc {
  83                 compatible = "intel,ich6-gpio";
  84                 u-boot,dm-pre-reloc;
  85                 reg = <0x40 0x20>;
  86                 bank-name = "C";
  87         };
  88
  89         gpiod {
  90                 compatible = "intel,ich6-gpio";
  91                 u-boot,dm-pre-reloc;
  92                 reg = <0x60 0x20>;
  93                 bank-name = "D";
  94         };
  95
  96         gpioe {
  97                 compatible = "intel,ich6-gpio";
  98                 u-boot,dm-pre-reloc;
  99                 reg = <0x80 0x20>;
 100                 bank-name = "E";
 101         };
 102
 103         gpiof {
 104                 compatible = "intel,ich6-gpio";
 105                 u-boot,dm-pre-reloc;
 106                 reg = <0xA0 0x20>;
 107                 bank-name = "F";
 108         };
 109
 110         pci {
 111                 compatible = "pci-x86";
 112                 #address-cells = <3>;
 113                 #size-cells = <2>;
 114                 u-boot,dm-pre-reloc;
 115                 ranges = <0x02000000 0x0 0x80000000 0x80000000 0 0x40000000
 116                           0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000
 117                           0x01000000 0x0 0x2000 0x2000 0 0xe000>;
 118
 119                 pch@1f,0 {
 120                         reg = <0x0000f800 0 0 0 0>;
 121                         compatible = "intel,pch9";
 122
 123                         irq-router {
 124                                 compatible = "intel,irq-router";
 125                                 intel,pirq-config = "ibase";
 126                                 intel,ibase-offset = <0x50>;
 127                                 intel,pirq-link = <8 8>;
 128                                 intel,pirq-mask = <0xdee0>;
 129                                 intel,pirq-routing = <
 130                                         /* BayTrail PCI devices */
 131                                         PCI_BDF(0, 2, 0) INTA PIRQA
 132                                         PCI_BDF(0, 3, 0) INTA PIRQA
 133                                         PCI_BDF(0, 16, 0) INTA PIRQA
 134                                         PCI_BDF(0, 17, 0) INTA PIRQA
 135                                         PCI_BDF(0, 18, 0) INTA PIRQA
 136                                         PCI_BDF(0, 19, 0) INTA PIRQA
 137                                         PCI_BDF(0, 20, 0) INTA PIRQA
 138                                         PCI_BDF(0, 21, 0) INTA PIRQA
 139                                         PCI_BDF(0, 22, 0) INTA PIRQA
 140                                         PCI_BDF(0, 23, 0) INTA PIRQA
 141                                         PCI_BDF(0, 24, 0) INTA PIRQA
 142                                         PCI_BDF(0, 24, 1) INTC PIRQC
 143                                         PCI_BDF(0, 24, 2) INTD PIRQD
 144                                         PCI_BDF(0, 24, 3) INTB PIRQB
 145                                         PCI_BDF(0, 24, 4) INTA PIRQA
 146                                         PCI_BDF(0, 24, 5) INTC PIRQC
 147                                         PCI_BDF(0, 24, 6) INTD PIRQD
 148                                         PCI_BDF(0, 24, 7) INTB PIRQB
 149                                         PCI_BDF(0, 26, 0) INTA PIRQA
 150                                         PCI_BDF(0, 27, 0) INTA PIRQA
 151                                         PCI_BDF(0, 28, 0) INTA PIRQA
 152                                         PCI_BDF(0, 28, 1) INTB PIRQB
 153                                         PCI_BDF(0, 28, 2) INTC PIRQC
 154                                         PCI_BDF(0, 28, 3) INTD PIRQD
 155                                         PCI_BDF(0, 29, 0) INTA PIRQA
 156                                         PCI_BDF(0, 30, 0) INTA PIRQA
 157                                         PCI_BDF(0, 30, 1) INTD PIRQD
 158                                         PCI_BDF(0, 30, 2) INTB PIRQB
 159                                         PCI_BDF(0, 30, 3) INTC PIRQC
 160                                         PCI_BDF(0, 30, 4) INTD PIRQD
 161                                         PCI_BDF(0, 30, 5) INTB PIRQB
 162                                         PCI_BDF(0, 31, 3) INTB PIRQB
 163
 164                                         /*
 165                                          * PCIe root ports downstream
 166                                          * interrupts
 167                                          */
 168                                         PCI_BDF(1, 0, 0) INTA PIRQA
 169                                         PCI_BDF(1, 0, 0) INTB PIRQB
 170                                         PCI_BDF(1, 0, 0) INTC PIRQC
 171                                         PCI_BDF(1, 0, 0) INTD PIRQD
 172                                         PCI_BDF(2, 0, 0) INTA PIRQB
 173                                         PCI_BDF(2, 0, 0) INTB PIRQC
 174                                         PCI_BDF(2, 0, 0) INTC PIRQD
 175                                         PCI_BDF(2, 0, 0) INTD PIRQA
 176                                         PCI_BDF(3, 0, 0) INTA PIRQC
 177                                         PCI_BDF(3, 0, 0) INTB PIRQD
 178                                         PCI_BDF(3, 0, 0) INTC PIRQA
 179                                         PCI_BDF(3, 0, 0) INTD PIRQB
 180                                         PCI_BDF(4, 0, 0) INTA PIRQD
 181                                         PCI_BDF(4, 0, 0) INTB PIRQA
 182                                         PCI_BDF(4, 0, 0) INTC PIRQB
 183                                         PCI_BDF(4, 0, 0) INTD PIRQC
 184                                 >;
 185                         };
 186
 187                         spi {
 188                                 #address-cells = <1>;
 189                                 #size-cells = <0>;
 190                                 compatible = "intel,ich-spi";
 191                                 spi-flash@0 {
 192                                         #address-cells = <1>;
 193                                         #size-cells = <1>;
 194                                         reg = <0>;
 195                                         compatible = "winbond,w25q64dw",
 196                                                 "spi-flash";
 197                                         memory-map = <0xff800000 0x00800000>;
 198                                         rw-mrc-cache {
 199                                                 label = "rw-mrc-cache";
 200                                                 reg = <0x006e0000 0x00010000>;
 201                                         };
 202                                 };
 203                         };
 204                 };
 205         };
 206
 207         fsp {
 208                 compatible = "intel,baytrail-fsp";
 209                 fsp,mrc-init-tseg-size = <0>;
 210                 fsp,mrc-init-mmio-size = <0x800>;
 211                 fsp,mrc-init-spd-addr1 = <0xa0>;
 212                 fsp,mrc-init-spd-addr2 = <0xa2>;
 213                 fsp,emmc-boot-mode = <2>;
 214                 fsp,enable-sdio;
 215                 fsp,enable-sdcard;
 216                 fsp,enable-hsuart1;
 217                 fsp,enable-spi;
 218                 fsp,enable-sata;
 219                 fsp,sata-mode = <1>;
 220                 fsp,enable-lpe;
 221                 fsp,lpss-sio-enable-pci-mode;
 222                 fsp,enable-dma0;
 223                 fsp,enable-dma1;
 224                 fsp,enable-i2c0;
 225                 fsp,enable-i2c1;
 226                 fsp,enable-i2c2;
 227                 fsp,enable-i2c3;
 228                 fsp,enable-i2c4;
 229                 fsp,enable-i2c5;
 230                 fsp,enable-i2c6;
 231                 fsp,enable-pwm0;
 232                 fsp,enable-pwm1;
 233                 fsp,igd-dvmt50-pre-alloc = <2>;
 234                 fsp,aperture-size = <2>;
 235                 fsp,gtt-size = <2>;
 236                 fsp,serial-debug-port-address = <0x3f8>;
 237                 fsp,serial-debug-port-type = <1>;
 238                 fsp,scc-enable-pci-mode;
 239                 fsp,os-selection = <4>;
 240                 fsp,emmc45-ddr50-enabled;
 241                 fsp,emmc45-retune-timer-value = <8>;
 242                 fsp,enable-igd;
 243         };
 244
 245         microcode {
 246                 update@0 {
 247 #include "microcode/m0230671117.dtsi"
 248                 };
 249                 update@1 {
 250 #include "microcode/m0130673322.dtsi"
 251                 };
 252                 update@2 {
 253 #include "microcode/m0130679901.dtsi"
 254                 };
 255         };
 256
 257 };